Move defaults from config_cmd_default.h to Kconfig

[platform/kernel/u-boot.git] / include / configs / ls1021atwr.h

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0a0bb5f..446d562 100644 (file)
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <config_cmd_default.h>
-
 #define CONFIG_LS102XA
 
 #define CONFIG_SYS_GENERIC_BOARD
@@ -35,6 +33,29 @@
 #define CONFIG_SYS_CLK_FREQ            100000000
 #define CONFIG_DDR_CLK_FREQ            100000000
 
+#define DDR_SDRAM_CFG                  0x470c0008
+#define DDR_CS0_BNDS                   0x008000bf
+#define DDR_CS0_CONFIG                 0x80014302
+#define DDR_TIMING_CFG_0               0x50550004
+#define DDR_TIMING_CFG_1               0xbcb38c56
+#define DDR_TIMING_CFG_2               0x0040d120
+#define DDR_TIMING_CFG_3               0x010e1000
+#define DDR_TIMING_CFG_4               0x00000001
+#define DDR_TIMING_CFG_5               0x03401400
+#define DDR_SDRAM_CFG_2                        0x00401010
+#define DDR_SDRAM_MODE                 0x00061c60
+#define DDR_SDRAM_MODE_2               0x00180000
+#define DDR_SDRAM_INTERVAL             0x18600618
+#define DDR_DDR_WRLVL_CNTL             0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2           0x05060607
+#define DDR_DDR_WRLVL_CNTL_3           0x05050505
+#define DDR_DDR_CDR1                   0x80040000
+#define DDR_DDR_CDR2                   0x00000001
+#define DDR_SDRAM_CLK_CNTL             0x02000000
+#define DDR_DDR_ZQ_CNTL                        0x89080600
+#define DDR_CS0_CONFIG_2               0
+#define DDR_SDRAM_CFG_MEM_EN           0x80000000
+
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
 #endif
@@ -73,7 +94,7 @@
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE           0x67f80000
+#define CONFIG_SYS_TEXT_BASE           0x60100000
 #endif
 
 #define CONFIG_NR_DRAM_BANKS           1
@@ -205,6 +226,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* EEPROM */
 #ifndef CONFIG_SD_BOOT
@@ -236,7 +258,6 @@
 #define FSL_QSPI_FLASH_NUM             2
 
 #define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
 
@@ -303,20 +324,35 @@
 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE      0x00001000      /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF  0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE      0x00001000      /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS         0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF    0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE                0x00010000      /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS                0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF   0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE       0x08000000      /* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#ifdef CONFIG_QSPI_BOOT
-#undef CONFIG_CMD_IMLS
-#else
-#define CONFIG_CMD_IMLS
-#endif
-
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
@@ -355,7 +391,6 @@
 #define CONFIG_SYS_MAXARGS             16      /* max number of command args */
 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_ENV_EXISTS
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MEMINFO
 #define CONFIG_CMD_MEMTEST