* Base addresses -- Note these are effective addresses where the actual
* resources get mapped (not physical addresses).
*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
-
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH0_SIZE 0x01000000
-#define CFG_FLASH0_ADDR (-CFG_FLASH0_SIZE)
-#define CFG_FLASH1_TOP 0xF8000000
-#define CFG_FLASH1_MAX_SIZE 0x08000000
-#define CFG_FLASH1_ADDR (CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE)
-#define CFG_FLASH_BASE CFG_FLASH1_ADDR /* start of FLASH */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_OCM_BASE 0xe0010000 /* ocm */
-#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
-#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CONFIG_SYS_FLASH0_SIZE 0x01000000
+#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
+#define CONFIG_SYS_FLASH1_TOP 0xF8000000
+#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
+#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
+#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
/* Don't change either of these */
-#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
-#define CFG_USB2D0_BASE 0xe0000100
-#define CFG_USB_DEVICE 0xe0000000
-#define CFG_USB_HOST 0xe0000400
-#define CFG_CPLD_BASE 0xc0000000
+#define CONFIG_SYS_USB2D0_BASE 0xe0000100
+#define CONFIG_SYS_USB_DEVICE 0xe0000000
+#define CONFIG_SYS_USB_HOST 0xe0000400
+#define CONFIG_SYS_CPLD_BASE 0xc0000000
/*
* Initial RAM & stack pointer
*/
/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
-#undef CFG_INIT_RAM_DCACHE
-#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
-#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+#undef CONFIG_SYS_INIT_RAM_DCACHE
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
+#define CONFIG_SYS_INIT_RAM_END (4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
/*
* Serial Port
*/
-#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
/*
* FLASH related
*/
-#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CFG_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
/*
* DDR SDRAM
*/
-#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
+#define CONFIG_SYS_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
#define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
-#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
/*
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C RTC */
#define CONFIG_RTC_M41T60 1
-#define CFG_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* I2C SYSMON (LM73) */
#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
-#define CFG_DTT_MAX_TEMP 70
-#define CFG_DTT_MIN_TEMP -30
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_MIN_TEMP -30
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME korat
-#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
-#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
+#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
+#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
- CFG_ROOTPATH \
+ CONFIG_SYS_BOOTFILE \
+ CONFIG_SYS_ROOTPATH \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
+#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
/* buffers & descriptors */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_CMD_USB
/* POST support */
-#define CONFIG_POST (CFG_POST_CACHE | \
- CFG_POST_CPU | \
- CFG_POST_ECC | \
- CFG_POST_ETHER | \
- CFG_POST_FPU | \
- CFG_POST_I2C | \
- CFG_POST_MEMORY | \
- CFG_POST_RTC | \
- CFG_POST_SPR | \
- CFG_POST_UART)
-
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_ECC | \
+ CONFIG_SYS_POST_ETHER | \
+ CONFIG_SYS_POST_FPU | \
+ CONFIG_SYS_POST_I2C | \
+ CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_RTC | \
+ CONFIG_SYS_POST_SPR | \
+ CONFIG_SYS_POST_UART)
+
+#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
+#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
/*
* Korat-specific options
*/
-#define CFG_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
+#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
/*
* PCI stuff
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
- /* CFG_PCI_MEMBASE */
+#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
+ /* CONFIG_SYS_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data have to be in the
* first 8 MB of memory, since this is the maximum mapped by the Linux kernel
* during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (NOR-FLASH) initialization */
-#if CFG_FLASH0_SIZE == 0x01000000
-#define CFG_EBC_PB0AP 0x04017300
-#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x0009A000)
-#elif CFG_FLASH0_SIZE == 0x04000000
-#define CFG_EBC_PB0AP 0x04017300
-#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x000DA000)
+#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
+#define CONFIG_SYS_EBC_PB0AP 0x04017300
+#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
+#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
+#define CONFIG_SYS_EBC_PB0AP 0x04017300
+#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
#else
-#error Unable to configure chip select for current CFG_FLASH0_SIZE
+#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
#endif
/* Memory Bank 1 (NOR-FLASH) initialization */
-#if CFG_FLASH1_MAX_SIZE == 0x08000000
-#define CFG_EBC_PB1AP 0x04017300
-#define CFG_EBC_PB1CR (CFG_FLASH1_ADDR | 0x000FA000)
+#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
+#define CONFIG_SYS_EBC_PB1AP 0x04017300
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
#else
-#error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE
+#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
#endif
/* Memory Bank 2 (CPLD) initialization */
-#define CFG_EBC_PB2AP 0x04017300
-#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
+#define CONFIG_SYS_EBC_PB2AP 0x04017300
+#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
/*
* GPIO Setup
* GPIO63 xxxx x x (reserved for trace port)
*/
-#define CFG_GPIO_ATMEGA_RESET_ 12
-#define CFG_GPIO_ATMEGA_SS_ 13
-#define CFG_GPIO_PHY0_FIBER_SEL 27
-#define CFG_GPIO_PHY1_FIBER_SEL 28
-#define CFG_GPIO_SFP0_PRESENT_ 30
-#define CFG_GPIO_SFP1_PRESENT_ 31
-#define CFG_GPIO_SFP0_TX_EN_ 32
-#define CFG_GPIO_SFP1_TX_EN_ 33
-#define CFG_GPIO_PHY0_EN 45
-#define CFG_GPIO_PHY1_EN 46
-#define CFG_GPIO_RESET_PRESSED_ 47
+#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
+#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
+#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
+#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
+#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
+#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
+#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
+#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
+#define CONFIG_SYS_GPIO_PHY0_EN 45
+#define CONFIG_SYS_GPIO_PHY1_EN 46
+#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
/*
* PPC440 GPIO Configuration
*/
-#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
projects / platform / kernel / u-boot.git / blobdiff