global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*

[platform/kernel/u-boot.git] / include / configs / kmcent2.h

diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 2e1459e..51ee686 100644 (file)
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -231,18 +231,18 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
 
 /* NAND Flash on IFC CS1*/
-#define CONFIG_SYS_NAND_BASE           0xfa000000
-#define CONFIG_SYS_NAND_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE              0xfa000000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT       (0x0f)
-#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT  (0x0f)
+#define CFG_SYS_NAND_CSPR      (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
                                CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
                                0x00000010 |       /* drive TE high */\
                                CSPR_MSEL_NAND |   /* MSEL = NAND */\
                                CSPR_V)            /* valid */
-#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64 * 1024) /* 64kB */
+#define CFG_SYS_NAND_AMASK     IFC_AMASK(64 * 1024) /* 64kB */
 
-#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+#define CFG_SYS_NAND_CSOR      (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
                                CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
                                CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
                                CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
@@ -253,30 +253,30 @@
                                CSOR_NAND_BCTLD)       /**/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0     (FTIM0_NAND_TCCST(0x3) | \
                                FTIM0_NAND_TWP(0x8) | \
                                FTIM0_NAND_TWCHT(0x3) | \
                                FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1     (FTIM1_NAND_TADLE(0x1e) | \
                                FTIM1_NAND_TWBE(0x1e) | \
                                FTIM1_NAND_TRR(0x6) | \
                                FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2     (FTIM2_NAND_TRAD(0x9) | \
                                FTIM2_NAND_TREH(0x5) | \
                                FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3  (FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3     (FTIM3_NAND_TWW(0x1e))
 
-#define CONFIG_SYS_CSPR1_EXT   CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1       CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1      CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1       CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0   CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1   CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2   CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3   CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT   CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1       CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1      CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1       CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0   CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1   CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2   CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3   CFG_SYS_NAND_FTIM3
 
 /* More NAND Flash Params */
-#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 
 /* QRIO on IFC CS2 */
 #define CONFIG_SYS_QRIO_BASE           0xfb000000