Convert CONFIG_SYS_NAND_ONFI_DETECTION to Kconfig

[platform/kernel/u-boot.git] / include / configs / km / pg-wcom-ls102xa.h

diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index a4cc477..1ce6ac9 100644 (file)
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -8,16 +8,9 @@
 
 #define CONFIG_SYS_FSL_CLK
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
 
@@ -26,12 +19,6 @@
                                          CONFIG_KM_RESERVED_PRAM) >> 10)
 
 #define CONFIG_SYS_CLK_FREQ            66666666
-/*
- * Take into account default implementation where DDR_FDBK_MULTI is consider as
- * configured for DDR_PLL = 2*MEM_PLL_RAT.
- * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
- */
-#define CONFIG_DDR_CLK_FREQ            (100000000 >> 1)
 
 #define PHYS_SDRAM                     0x80000000
 #define PHYS_SDRAM_SIZE                        (1u * 1024 * 1024 * 1024)
@@ -42,8 +29,6 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
-#define CONFIG_DDR_SPD
-
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define SPD_EEPROM_ADDRESS             0x54
 
@@ -130,8 +115,6 @@
                                        | CSOR_NAND_TRHZ_40 \
                                        | CSOR_NAND_BCTLD)
 
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
 #define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x3) | \
                                        FTIM0_NAND_TWP(0x8) | \
                                        FTIM0_NAND_TWCHT(0x3) | \
@@ -156,7 +139,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
 
 /* QRIO FPGA Definitions */
 #define CONFIG_SYS_QRIO_BASE           0x70000000
@@ -191,9 +173,7 @@
 /*
  * I2C
  */
-#define CONFIG_SYS_I2C_LEGACY
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED           100000
 
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_MAX_HOPS                1
@@ -224,8 +204,6 @@
  * Miscellaneous configurable options
  */
 
-#define CONFIG_SYS_LOAD_ADDR           0x82000000
-
 #define CONFIG_LS102XA_STREAM_ID
 
 #define CONFIG_SYS_INIT_SP_OFFSET \