| CSOR_NAND_TRHZ_40 \
| CSOR_NAND_BCTLD)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* QRIO FPGA Definitions */
#define CONFIG_SYS_QRIO_BASE 0x70000000