#undef CONFIG_CONS_NONE /* It's not on external UART */
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-#define CFG_BCSR 0xFA000000
+#define CONFIG_SYS_BCSR 0xFA000000
/*
* Select ethernet configuration
* - BDs/buffers on 60x bus
* - Full duplex
*/
-#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
-#define CFG_CPMFCR_RAMTYPE 0
-#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
+#define CONFIG_SYS_CPMFCR_RAMTYPE 0
+#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#elif (CONFIG_ETHER_INDEX == 2)
* - BDs/buffers on 60x bus
* - Full duplex
*/
-#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#define CFG_CPMFCR_RAMTYPE 0
-#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE 0
+#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif /* CONFIG_ETHER_INDEX */
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 0 /* Not used - implemented in BCSR */
-#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
-#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04)
-#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1)
+#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
+#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
-#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
- else *(vu_char *)(CFG_BCSR + 8) &= 0xFE
+#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
+ else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
-#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
- else *(vu_char *)(CFG_BCSR + 8) &= 0xFD
+#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
+ else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
#define MIIDELAY udelay(1)
/*
* Miscellaneous configurable options
*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CFG_FLASH_BASE 0xFF800000
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE 0xFF800000
+#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-#define CFG_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
#if defined(CONFIG_CMD_JFFS2)
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
-#define CFG_JFFS2_FIRST_SECTOR 0
-#define CFG_JFFS2_LAST_SECTOR 62
-#define CFG_JFFS2_SORT_FRAGMENTS
-#define CFG_JFFS_CUSTOM_PART
+#define CONFIG_SYS_JFFS2_FIRST_BANK 0
+#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
+#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS_CUSTOM_PART
#endif
#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CFG_I2C_SPEED 100000 /* I2C speed */
-#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
#endif
-#define CFG_MONITOR_BASE TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
#endif
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
#define CONFIG_ENV_IS_IN_FLASH
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#endif /* CONFIG_ENV_IS_IN_FLASH */
-#define CFG_DEFAULT_IMMR 0x00010000
+#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
-#define CFG_IMMR 0xF0000000
+#define CONFIG_SYS_IMMR 0xF0000000
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Hard reset configuration word */
-#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
+#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
/* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-#define CFG_HID0_INIT 0
-#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
+#define CONFIG_SYS_HID0_INIT 0
+#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-#define CFG_HID2 0
+#define CONFIG_SYS_HID2 0
-#define CFG_SIUMCR 0x01240200
-#define CFG_SYPCR 0xFFFF0683
-#define CFG_BCR 0x00000000
-#define CFG_SCCR SCCR_DFBRG01
+#define CONFIG_SYS_SIUMCR 0x01240200
+#define CONFIG_SYS_SYPCR 0xFFFF0683
+#define CONFIG_SYS_BCR 0x00000000
+#define CONFIG_SYS_SCCR SCCR_DFBRG01
-#define CFG_RMR RMR_CSRE
-#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR 0
+#define CONFIG_SYS_RMR RMR_CSRE
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR 0
-#define CFG_MPTPR 0x1300
-#define CFG_PSDMR 0x82672522
-#define CFG_PSRT 0x4B
+#define CONFIG_SYS_MPTPR 0x1300
+#define CONFIG_SYS_PSDMR 0x82672522
+#define CONFIG_SYS_PSRT 0x4B
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841)
-#define CFG_SDRAM_OR 0xFF0030C0
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
+#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
-#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
-#define CFG_OR0_PRELIM 0xFF8008C2
-#define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801)
-#define CFG_OR2_PRELIM 0xFFF00864
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
-#define CFG_RESET_ADDRESS 0xC0000000
+#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
#endif /* __CONFIG_H */
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