Prepare v2023.10

[platform/kernel/u-boot.git] / include / configs / da850evm.h

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index f8ba4e8..cef4042 100644 (file)
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -17,13 +17,13 @@
 /*
  * SoC Configuration
  */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_OSCIN_FREQ          24000000
-#define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK            clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_OSCIN_FREQ             24000000
+#define CFG_SYS_TIMERBASE              DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK               clk_get(DAVINCI_AUXCLK_CLKID)
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_DV_NOR_BOOT_CFG     (0x11)
+#define CFG_SYS_DV_NOR_BOOT_CFG        (0x11)
 #endif
 
 /*
@@ -31,12 +31,12 @@
  */
 #define PHYS_SDRAM_1           DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE      (64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 /* memtest start addr */
 
 /* memtest will be run on 16MB */
 
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (      \
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
        DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
        DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
        DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
@@ -47,17 +47,17 @@
  * PLL configuration
  */
 
-#define CONFIG_SYS_DA850_PLL0_PLLM     24
-#define CONFIG_SYS_DA850_PLL1_PLLM     21
+#define CFG_SYS_DA850_PLL0_PLLM     24
+#define CFG_SYS_DA850_PLL1_PLLM     21
 
 /*
  * DDR2 memory configuration
  */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
                                        DV_DDR_PHY_EXT_STRBEN | \
                                        (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDBCR (          \
+#define CFG_SYS_DA850_DDR2_SDBCR (             \
        (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
        (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
        (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
@@ -67,9 +67,9 @@
        (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 
 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR (         \
+#define CFG_SYS_DA850_DDR2_SDTIMR (            \
        (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
        (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
        (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
@@ -79,7 +79,7 @@
        (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
        (0 << DV_DDR_SDTMR1_WTR_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (                \
+#define CFG_SYS_DA850_DDR2_SDTIMR2 (           \
        (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
        (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
        (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
@@ -88,20 +88,20 @@
        (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
        (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
-#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+#define CFG_SYS_DA850_DDR2_SDRCR    0x00000494
+#define CFG_SYS_DA850_DDR2_PBBPR    0x30
 
 /*
  * Serial Driver info
  */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK    clk_get(DAVINCI_UART2_CLKID)
 
-#define CONFIG_SYS_SPI_CLK             clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_CLK                clk_get(DAVINCI_SPI1_CLKID)
 
 /*
  * I2C Configuration
  */
-#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR   0x20
 
 /*
  * Flash & Environment
@@ -125,7 +125,7 @@
 #endif
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE          DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define CFG_SYS_FLASH_BASE             DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 #define PHYS_FLASH_SIZE                        (8 << 20) /* Flash size 8MB */
 #endif
 
@@ -137,16 +137,15 @@
  * Linux Information
  */
 #define LINUX_BOOT_PARAM_ADDR  (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_HWCONFIG                /* enable hwconfig */
 
 #define DEFAULT_LINUX_BOOT_ENV \
        "loadaddr=0xc0700000\0" \
        "fdtaddr=0xc0600000\0" \
        "scriptaddr=0xc0600000\0"
 
-#include <environment/ti/mmc.h>
+#include <env/ti/mmc.h>
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
        DEFAULT_LINUX_BOOT_ENV \
        DEFAULT_MMC_TI_ARGS \
        "bootpart=0:2\0" \
@@ -166,7 +165,7 @@
 /* Load U-Boot Image From MMC */
 
 /* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE          0xc0000000
+#define CFG_SYS_SDRAM_BASE             0xc0000000
 
 #include <asm/arch/hardware.h>