treewide: mem: Move mtest related defines to Kconfig

[platform/kernel/u-boot.git] / include / configs / colibri_pxa270.h

diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 484483d..29827f1 100644 (file)
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Toradex Colibri PXA270 configuration file
  *
  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef        __CONFIG_H
@@ -17,18 +16,11 @@
 /* Avoid overwriting factory configuration block */
 #define CONFIG_BOARD_SIZE_LIMIT                0x40000
 
-/* We will never enable dcache because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define CONFIG_DISPLAY_BOARDINFO_LATE  /* Calls show_board_info() */
-
 /*
  * Environment settings
  */
 #define        CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define        CONFIG_SYS_MALLOC_LEN           (128 * 1024)
-#define        CONFIG_ARCH_CPU_INIT
 #define        CONFIG_BOOTCOMMAND                                              \
        "if fatload mmc 0 0xa0000000 uImage; then "                     \
                "bootm 0xa0000000; "                                    \
@@ -88,16 +80,12 @@
 /*
  * DRAM Map
  */
-#define        CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
 #define        PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 #define        PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
 
 #define        CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 #define        CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
 
-#define CONFIG_SYS_MEMTEST_START       0xa0400000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM */
-
 #define        CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
 #define        CONFIG_SYS_INIT_SP_ADDR         0x5c010000
@@ -110,8 +98,6 @@
 #define        PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
 #define        CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 
-#define        CONFIG_SYS_FLASH_CFI
-#define        CONFIG_FLASH_CFI_DRIVER         1
 #define        CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 
 #define        CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
@@ -121,19 +107,12 @@
 #define        CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 #define        CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
 #define        CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
-
-#define        CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
-#define        CONFIG_SYS_FLASH_PROTECTION             1
 #endif
 
 #define        CONFIG_SYS_MONITOR_BASE         0x0
 #define        CONFIG_SYS_MONITOR_LEN          0x40000
 
 /* Skip factory configuration block */
-#define        CONFIG_ENV_ADDR                 \
-                       (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
-#define        CONFIG_ENV_SIZE                 0x40000
-#define        CONFIG_ENV_SECT_SIZE            0x40000
 
 /*
  * GPIO settings