#error No card type defined!
#endif
-/*
- * CONFIG_RAM defines if u-boot is loaded via BDM (or started from
- * a different bootloader that has already performed RAM setup) or
- * started directly from flash, which is the regular case for production
- * boards.
- */
-#ifdef CONFIG_RAM
-#define CONFIG_MONITOR_IS_IN_RAM
-#define ENABLE_JFFS 0
-#else
-#define ENABLE_JFFS 1
-#endif
-
/* I2C */
/*
* interface etc.
*/
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3)
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/*
* Define baudrate for UART1 (console output, tftp, ...)
* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * CFG_SYS_BAUDRATE_TABLE defines values that can be selected
* in u-boot command interface
*/
-#define CONFIG_SYS_UART_PORT (2)
-#define CONFIG_SYS_UART2_ALT3_GPIO
-
-/*
- * Watchdog configuration; Watchdog is disabled for running from RAM
- * and set to highest possible value else. Beware there is no check
- * in the watchdog code to validate the timeout value set here!
- */
-
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */
-#endif
-
-/*
- * Configuration for environment
- * Environment is located in the last sector of the flash
- */
-
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#else
-/*
- * environment in RAM - This is used to use a single PC-based application
- * to load an image, load U-Boot, load an environment and then start U-Boot
- * to execute the commands from the environment. Feedback is done via setting
- * and reading memory locations.
- */
-#endif
+#define CFG_SYS_UART_PORT (2)
+#define CFG_SYS_UART2_ALT3_GPIO
/* here we put our FPGA configuration... */
* u-boot: 'set' command
*/
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"loaderversion=11\0" \
"card_id="__stringify(ASTRO_ID)"\0" \
"alterafile=0\0" \
* it needs non-blocking CFI routines.
*/
-#define CONFIG_SYS_FPGA_WAIT 1000
+#define CFG_SYS_FPGA_WAIT 1000
/* End of user parameters to be customized */
/* Base register address */
-#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
/* System Conf. Reg. & System Protection Reg. */
-#define CONFIG_SYS_SCR 0x0003;
-#define CONFIG_SYS_SPR 0xffff;
+#define CFG_SYS_SCR 0x0003;
+#define CFG_SYS_SPR 0xffff;
/*
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/*
* Chipselect bank definitions
* CS4 - unused
* CS5 - unused
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x00ff0001
-#define CONFIG_SYS_CS0_CTRL 0x00001fc0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x00ff0001
+#define CFG_SYS_CS0_CTRL 0x00001fc0
-#define CONFIG_SYS_CS1_BASE 0x01000000
-#define CONFIG_SYS_CS1_MASK 0x00ff0001
-#define CONFIG_SYS_CS1_CTRL 0x00001fc0
+#define CFG_SYS_CS1_BASE 0x01000000
+#define CFG_SYS_CS1_MASK 0x00ff0001
+#define CFG_SYS_CS1_CTRL 0x00001fc0
-#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK 0x00ff0001
-#define CONFIG_SYS_CS2_CTRL 0x0000fec0
+#define CFG_SYS_CS2_BASE 0x20000000
+#define CFG_SYS_CS2_MASK 0x00ff0001
+#define CFG_SYS_CS2_CTRL 0x0000fec0
-#define CONFIG_SYS_CS3_BASE 0x21000000
-#define CONFIG_SYS_CS3_MASK 0x00ff0001
-#define CONFIG_SYS_CS3_CTRL 0x0000fec0
+#define CFG_SYS_CS3_BASE 0x21000000
+#define CFG_SYS_CS3_MASK 0x00ff0001
+#define CFG_SYS_CS3_CTRL 0x0000fec0
-#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CFG_SYS_FLASH_BASE 0x00000000
/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
- (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+ (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_SIZE 0x2000000
+#define CFG_SYS_FLASH_SIZE 0x2000000
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
env/embedded.o(.text*)
-#if ENABLE_JFFS
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40
-#endif
-
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
+
#endif /* _CONFIG_ASTRO_MCF5373L_H */
projects / platform / kernel / u-boot.git / blobdiff