ppc4xx: Remove cache definition from 4xx board config files

[platform/kernel/u-boot.git] / include / configs / acadia.h

diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index e3f6e2c..dc322dd 100644 (file)
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -385,15 +385,6 @@
 #define CFG_NAND_SELECT_DEVICE  1      /* nand driver supports mutipl. chips   */
 
 /*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                16384           /* For AMCC 405EZ CPU           */
-#define CFG_CACHELINE_SIZE     32              /* ...                          */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5               /* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)