Convert CONFIG_SYS_MALLOC_LEN to Kconfig

[platform/kernel/u-boot.git] / include / configs / UCP1020.h

diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 5086077..22b8c3f 100644 (file)
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -13,6 +13,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <linux/stringify.h>
+
 /*** Arcturus FirmWare Environment */
 
 #define MAX_SERIAL_SIZE 15
@@ -30,9 +32,6 @@
 #define FWENV_TYPE     FWENV_NOR_FLASH
 
 #if (FWENV_TYPE == FWENV_MMC)
-#ifndef CONFIG_SYS_MMC_ENV_DEV
-#define CONFIG_SYS_MMC_ENV_DEV 1
-#endif
 #define FWENV_ADDR1 -1
 #define FWENV_ADDR2 -1
 #define FWENV_ADDR3 -1
@@ -146,13 +145,10 @@
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
 #endif
 
-#define CONFIG_ENV_OVERWRITE
-
 #define CONFIG_SYS_SATA_MAX_DEVICE     2
 #define CONFIG_LBA48
 
 #define CONFIG_SYS_CLK_FREQ    66666666
-#define CONFIG_DDR_CLK_FREQ    66666666
 
 #define CONFIG_HWCONFIG
 
@@ -174,11 +170,6 @@
 #endif
 
 /* DDR Setup */
-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif
 #define CONFIG_SYS_SPD_BUS_NUM 1
 
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_512M
@@ -207,11 +198,7 @@
 #define CONFIG_SYS_DDR_SR_CNTR         0x00000000
 #define CONFIG_SYS_DDR_RCW_1           0x00000000
 #define CONFIG_SYS_DDR_RCW_2           0x00000000
-#ifdef CONFIG_DDR_ECC_ENABLE
 #define CONFIG_SYS_DDR_CONTROL         0xE70C0000      /* Type = DDR3 & ECC */
-#else
-#define CONFIG_SYS_DDR_CONTROL         0xC70C0000      /* Type = DDR3 */
-#endif
 #define CONFIG_SYS_DDR_CONTROL_2       0x04401050
 #define CONFIG_SYS_DDR_TIMING_4                0x00220001
 #define CONFIG_SYS_DDR_TIMING_5                0x03402400
@@ -225,8 +212,6 @@
 #define CONFIG_SYS_DDR_MODE_2          0x8000c000
 #define CONFIG_SYS_DDR_INTERVAL                0x0C300000
 
-#undef CONFIG_CLOCKS_IN_MHZ
-
 /*
  * Memory map
  *
@@ -279,7 +264,6 @@
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN  (1024 * 1024)/* Reserved for malloc */
 
 #define CONFIG_SYS_PMC_BASE    0xff980000
 #define CONFIG_SYS_PMC_BASE_PHYS       CONFIG_SYS_PMC_BASE
@@ -315,14 +299,6 @@
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR + 0x4600)
 
 /* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED       400000
-#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED      400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
 #define CONFIG_SYS_SPD_BUS_NUM         1 /* For rom_loc and flash bank */
 
@@ -369,7 +345,6 @@
  */
 #if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV 0
 #endif
 
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */
@@ -401,7 +376,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
 #define CONFIG_SYS_HZ          1000    /* decrementer freq: 1ms tick */
 
 /*
@@ -454,9 +428,6 @@
 #define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin /* U-Boot image on TFTP server */
 
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR                1000000
-
 #if defined(CONFIG_DONGLE)
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                                       \