/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
*/
/*
#include <linux/stringify.h>
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
/* High Level Configuration Options */
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS }
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT (0xf)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
+#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
+#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
-#define CONFIG_HWCONFIG
-
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port
*/
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#endif
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/*
* I2C
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 18
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 18
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 18
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 18
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
*/
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define __USB_PHY_TYPE utmi
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:" \
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
"bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
projects / platform / kernel / u-boot.git / blobdiff