global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*

[platform/kernel/u-boot.git] / include / configs / T208xQDS.h

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 0819550..47f4990 100644 (file)
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -29,9 +29,9 @@
 #define BOOT_PAGE_OFFSET               0x27000
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST     0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE       (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST        0x00200000
+#define CFG_SYS_NAND_U_BOOT_START      0x00200000
 #endif
 
 #ifdef CONFIG_SPIFLASH
@@ -166,17 +166,17 @@
 #define CONFIG_SYS_CS3_FTIM3           0x0
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE           0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE              0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT       (0xf)
-#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT  (0xf)
+#define CFG_SYS_NAND_CSPR      (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
                                | CSPR_MSEL_NAND         /* MSEL = NAND */ \
                                | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK     IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR      (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
                                | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
@@ -185,30 +185,30 @@
                                | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0             (FTIM0_NAND_TCCST(0x07) | \
                                        FTIM0_NAND_TWP(0x18)    | \
                                        FTIM0_NAND_TWCHT(0x07)  | \
                                        FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1          (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1             (FTIM1_NAND_TADLE(0x32) | \
                                        FTIM1_NAND_TWBE(0x39)   | \
                                        FTIM1_NAND_TRR(0x0e)    | \
                                        FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2          (FTIM2_NAND_TRAD(0x0f)  | \
+#define CFG_SYS_NAND_FTIM2             (FTIM2_NAND_TRAD(0x0f)  | \
                                        FTIM2_NAND_TREH(0x0a)   | \
                                        FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3          0x0
+#define CFG_SYS_NAND_FTIM3             0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT           CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0               CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0              CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0               CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
@@ -242,14 +242,14 @@
 #define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2               CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2              CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2               CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1           CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2              CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2               CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0           CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1           CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2           CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3           CFG_SYS_NAND_FTIM3
 #endif
 
 #define CONFIG_HWCONFIG