/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
*/
#ifndef __CONFIG_H
#ifdef CONFIG_MTD_RAW_NAND
#ifdef CONFIG_NXP_ESBC
-#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
-/*
- * HDR would be appended at end of image and copied to DDR along
- * with U-Boot image.
- */
-#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
- CONFIG_U_BOOT_HDR_SIZE)
+#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + (16 << 10))
#else
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
+#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
+#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
/* High Level Configuration Options */
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
* These can be toggled for performance analysis, otherwise use default.
*/
#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
/*
* Config the L3 Cache as L3 SRAM
/*
* DDR Setup
*/
-#define CONFIG_VERY_BIG_RAM
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* CPLD on IFC */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
-#if defined(CONFIG_TARGET_T1042RDB_PI)
-#define CPLD_DIU_SEL_DFP 0x80
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
#define CPLD_DIU_SEL_DFP 0xc0
#endif
-#if defined(CONFIG_TARGET_T1040D4RDB)
-#define CPLD_INT_MASK_ALL 0xFF
-#define CPLD_INT_MASK_THERM 0x80
-#define CPLD_INT_MASK_DVI_DFP 0x40
-#define CPLD_INT_MASK_QSGMII1 0x20
-#define CPLD_INT_MASK_QSGMII2 0x10
-#define CPLD_INT_MASK_SGMI1 0x08
-#define CPLD_INT_MASK_SGMI2 0x04
-#define CPLD_INT_MASK_TDMR1 0x02
-#define CPLD_INT_MASK_TDMR2 0x01
-#endif
-
#define CFG_SYS_CPLD_BASE 0xffdf0000
#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
#define CFG_SYS_CSPR2_EXT (0xf)
#endif
/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
* open - index 2
* shorted - index 1
*/
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#endif
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x8
-#if defined(CONFIG_TARGET_T1042RDB_PI) || \
- defined(CONFIG_TARGET_T1040D4RDB) || \
- defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
/*
* RTC configuration
*/
#define CFG_SYS_I2C_RTC_ADDR 0x68
-/*DVI encoder*/
-#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
#endif
/*
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CFG_SYS_SGMII1_PHY_ADDR 0x03
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CFG_SYS_SGMII1_PHY_ADDR 0x01
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
#define CFG_SYS_SGMII1_PHY_ADDR 0x02
#define CFG_SYS_SGMII2_PHY_ADDR 0x03
#define CFG_SYS_SGMII3_PHY_ADDR 0x01
#endif
-#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CFG_SYS_RGMII1_PHY_ADDR 0x04
-#define CFG_SYS_RGMII2_PHY_ADDR 0x05
-#else
#define CFG_SYS_RGMII1_PHY_ADDR 0x01
#define CFG_SYS_RGMII2_PHY_ADDR 0x02
#endif
-/* Enable VSC9953 L2 Switch driver on T1040 SoC */
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
-#ifdef CONFIG_TARGET_T1040RDB
-#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
-#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
-#else
-#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
-#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
-#endif
-#endif
-#endif
-
/*
* Miscellaneous configurable options
*/
/*
* Environment Configuration
*/
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
#define __USB_PHY_TYPE utmi
#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
-#ifdef CONFIG_TARGET_T1040RDB
-#define FDTFILE "t1040rdb/t1040rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB_PI)
-#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB)
-#define FDTFILE "t1042rdb/t1042rdb.dtb"
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
projects / platform / kernel / u-boot.git / blobdiff