Prepare v2023.10

[platform/kernel/u-boot.git] / include / configs / T104xRDB.h

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 7a5bf93..01db298 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 #ifndef __CONFIG_H
@@ -29,7 +29,7 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
+#define        CFG_RESET_VECTOR_ADDRESS                0x30000FFC
 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE  (768 << 10)
 #define CFG_SYS_SPI_FLASH_U_BOOT_DST           (0x30000000)
 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
@@ -37,7 +37,7 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define        CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
+#define        CFG_RESET_VECTOR_ADDRESS                0x30000FFC
 #define CFG_SYS_MMC_U_BOOT_SIZE        (768 << 10)
 #define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
 #define CFG_SYS_MMC_U_BOOT_START       (0x30000000)
@@ -48,8 +48,8 @@
 
 /* High Level Configuration Options */
 
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS       0xeffffffc
 #endif
 
 #define CFG_SYS_NUM_CPC                CONFIG_SYS_NUM_DDR_CTLRS
@@ -127,24 +127,10 @@
 #define CPLD_LBMAP_RESET               0xFF
 #define CPLD_LBMAP_SHIFT               0x03
 
-#if defined(CONFIG_TARGET_T1042RDB_PI)
-#define CPLD_DIU_SEL_DFP               0x80
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 #define CPLD_DIU_SEL_DFP               0xc0
 #endif
 
-#if defined(CONFIG_TARGET_T1040D4RDB)
-#define CPLD_INT_MASK_ALL              0xFF
-#define CPLD_INT_MASK_THERM            0x80
-#define CPLD_INT_MASK_DVI_DFP          0x40
-#define CPLD_INT_MASK_QSGMII1          0x20
-#define CPLD_INT_MASK_QSGMII2          0x10
-#define CPLD_INT_MASK_SGMI1            0x08
-#define CPLD_INT_MASK_SGMI2            0x04
-#define CPLD_INT_MASK_TDMR1            0x02
-#define CPLD_INT_MASK_TDMR2            0x01
-#endif
-
 #define CFG_SYS_CPLD_BASE      0xffdf0000
 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
 #define CFG_SYS_CSPR2_EXT      (0xf)
@@ -252,7 +238,9 @@
  * open - index 2
  * shorted - index 1
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK            (get_bus_freq(0)/2)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -266,9 +254,7 @@
 #define I2C_MUX_PCA_ADDR                0x70
 #define I2C_MUX_CH_DEFAULT      0x8
 
-#if defined(CONFIG_TARGET_T1042RDB_PI) || \
-       defined(CONFIG_TARGET_T1040D4RDB)       || \
-       defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 /*
  * RTC configuration
  */
@@ -350,36 +336,16 @@
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_FMAN_ENET
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CFG_SYS_SGMII1_PHY_ADDR             0x03
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CFG_SYS_SGMII1_PHY_ADDR             0x01
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 #define CFG_SYS_SGMII1_PHY_ADDR             0x02
 #define CFG_SYS_SGMII2_PHY_ADDR             0x03
 #define CFG_SYS_SGMII3_PHY_ADDR             0x01
 #endif
 
-#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CFG_SYS_RGMII1_PHY_ADDR             0x04
-#define CFG_SYS_RGMII2_PHY_ADDR             0x05
-#else
 #define CFG_SYS_RGMII1_PHY_ADDR             0x01
 #define CFG_SYS_RGMII2_PHY_ADDR             0x02
 #endif
 
-/* Enable VSC9953 L2 Switch driver on T1040 SoC */
-#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
-#ifdef CONFIG_TARGET_T1040RDB
-#define CFG_SYS_FM1_QSGMII11_PHY_ADDR  0x04
-#define CFG_SYS_FM1_QSGMII21_PHY_ADDR  0x08
-#else
-#define CFG_SYS_FM1_QSGMII11_PHY_ADDR  0x08
-#define CFG_SYS_FM1_QSGMII21_PHY_ADDR  0x0c
-#endif
-#endif
-#endif
-
 /*
  * Miscellaneous configurable options
  */
@@ -402,19 +368,11 @@
 #define __USB_PHY_TYPE utmi
 #define RAMDISKFILE    "t104xrdb/ramdisk.uboot"
 
-#ifdef CONFIG_TARGET_T1040RDB
-#define FDTFILE                "t1040rdb/t1040rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB_PI)
-#define FDTFILE                "t1042rdb_pi/t1042rdb_pi.dtb"
-#elif defined(CONFIG_TARGET_T1042RDB)
-#define FDTFILE                "t1042rdb/t1042rdb.dtb"
-#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define FDTFILE                "t1042rdb/t1040d4rdb.dtb"
-#elif defined(CONFIG_TARGET_T1042D4RDB)
+#if defined(CONFIG_TARGET_T1042D4RDB)
 #define FDTFILE                "t1042rdb/t1042d4rdb.dtb"
 #endif
 
-#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+#define        CFG_EXTRA_ENV_SETTINGS                          \
        "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\