Merge with git://www.denx.de/git/u-boot.git

[platform/kernel/u-boot.git] / include / configs / PLU405.h

diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 5470373..4acbcd5 100644 (file)
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -96,7 +96,6 @@
 #define CONFIG_SUPPORT_VFAT
 
 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
-#define CONFIG_AUTO_UPDATE_SHOW 1       /* use board show routine       */
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
@@ -168,36 +167,15 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_NAND_LEGACY
+#define CFG_NAND_BASE_LIST     { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS          1
+#define CFG_MAX_NAND_DEVICE    1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US      25
 
-#define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN    0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE  (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 
@@ -276,11 +254,6 @@
 
 #define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK   0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS    1           /* ! second bank contains U-Boot */
-#endif
-
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
@@ -306,9 +279,6 @@
 #define CFG_ENV_SIZE           0x700   /* 2048 bytes may be used for env vars*/
                                   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CFG_NVRAM_BASE_ADDR    0xF0000500              /* NVRAM base address   */
-#define CFG_NVRAM_SIZE         242                     /* NVRAM size           */
-
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
@@ -317,7 +287,7 @@
 #define CFG_I2C_SLAVE          0x7F
 
 #define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT24WC08             */
-#if 1 /* test-only */
+
 /* CAT24WC08/16... */
 #define CFG_I2C_EEPROM_ADDR_LEN 1      /* Bytes of address             */
 /* mask of address bits that overflow into the "EEPROM chip address"   */
@@ -325,15 +295,6 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
                                        /* 16 byte page write mode using*/
                                        /* last 4 bits of the address   */
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2      /* Bytes of address             */
-/* mask of address bits that overflow into the "EEPROM chip address"   */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5   /* The Catalyst CAT24WC32 has   */
-                                       /* 32 byte page write mode using*/
-                                       /* last 5 bits of the address   */
-#endif
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE