ppc4xx: Remove cache definition from 4xx board config files

[platform/kernel/u-boot.git] / include / configs / PCI405.h

diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index d6e7082..e70c0d3 100644 (file)
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -251,15 +251,6 @@
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                8192    /* For AMCC 405 CPUs                    */
-#define CFG_CACHELINE_SIZE     32      /* ...                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
-#endif
-
 /*
  * Init Memory Controller:
  *