/*
* 15 MHz - CPU minimum clock
*/
-#define CFG_8xx_CPUCLK_MIN 15000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000
/*
* 133 MHz - CPU maximum clock
*/
-#define CFG_8xx_CPUCLK_MAX 133000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
-#define CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN CONFIG_8xx_OSCLK
+#define CONFIG_SYS_MEASURE_CPUCLK
+#define CONFIG_SYS_8XX_XIN CONFIG_8xx_OSCLK
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#define FEC_ENET
#define CONFIG_MII
-#define CFG_DISCOVER_PHY 1
+#define CONFIG_SYS_DISCOVER_PHY 1
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CFG_I2C_SPEED 100000 /* 100 kHz */
-#define CFG_I2C_SLAVE 0x7f
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7f
/*
* Software (bit-bang) I2C driver configuration
#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR 0x51
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
/*
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-#define CFG_LOAD_ADDR 0x00100000
+#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
-#define CFG_IMMR 0xF0000000
-#define CFG_IMMR_SIZE ((uint)(64 * 1024))
+#define CONFIG_SYS_IMMR 0xF0000000
+#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0x40000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CFG_RESET_ADDRESS 0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*
* NAND flash support
*/
-#define CFG_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
/*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
-#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
*/
-#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
-#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
-#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
+#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
SCCR_DFLCD000 | SCCR_DFALCD00)
*-----------------------------------------------------------------------
*
*/
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
/*
* Init Memory Controller:
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/* FLASH timing: Default value of OR0 after reset */
-#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
OR_SCY_15_CLK | OR_TRLX)
-#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
/*
* BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
* rev2 only uses the chipselect
*/
-#define CFG_NAND_BASE 0x50000000
-#define CFG_NAND_SIZE 0x04000000
+#define CONFIG_SYS_NAND_BASE 0x50000000
+#define CONFIG_SYS_NAND_SIZE 0x04000000
-#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
-#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
+#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
+#define CONFIG_SYS_OR2_PRELIM (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI )
/*
* BR3 and OR3 (SDRAM)
/*
* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
*/
-#define CFG_OR_TIMING_SDRAM 0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
-#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
/*
* BR4 and OR4 (CPLD)
*/
-#define CFG_CPLD_BASE 0x80000000 /* CPLD */
-#define CFG_CPLD_SIZE 0x10000 /* only 16 used */
+#define CONFIG_SYS_CPLD_BASE 0x80000000 /* CPLD */
+#define CONFIG_SYS_CPLD_SIZE 0x10000 /* only 16 used */
-#define CFG_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
OR_SCY_1_CLK)
-#define CFG_BR4_PRELIM ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR4_PRELIM (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
+#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD)
/*
* BR5 and OR5 (SRAM)
*/
-#define CFG_SRAM_BASE 0x60000000
-#define CFG_SRAM_SIZE 0x00080000
+#define CONFIG_SYS_SRAM_BASE 0x60000000
+#define CONFIG_SYS_SRAM_SIZE 0x00080000
-#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+#define CONFIG_SYS_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
+#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR5_PRELIM (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM)
#if defined(CONFIG_CP850)
/*
* BR6 and OR6 (DPRAM) - only on CP850
*/
-#define CFG_OR6_PRELIM 0xffff8170
-#define CFG_BR6_PRELIM 0xa0000401
+#define CONFIG_SYS_OR6_PRELIM 0xffff8170
+#define CONFIG_SYS_BR6_PRELIM 0xa0000401
#define DPRAM_BASE_ADDR 0xa0000000
#define CONFIG_MISC_INIT_R 1
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
-#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
-#define CFG_MAMR_PTA 39
+#define CONFIG_SYS_MAMR_PTA 39
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
-#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
* MBMR settings for NAND flash
*/
-#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
+#define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X )
/*
* Internal Definitions
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