#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
#endif
/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-
-/*
* Only possible on E500 Version 2 or newer cores.
*/
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xe0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
+#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
+#define CFG_SYS_FLASH_BANKS_LIST \
+ {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
/*
* SDRAM on the Local Bus
*/
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
#else
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* Common settings for all Local Bus SDRAM commands.
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
+#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| LSDMR_PRETOACT7 \
| LSDMR_ACTTORW7 \
| LSDMR_BL8 \
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
-#define CONFIG_FSL_CADMUS
-
#define CADMUS_BASE_ADDR 0xf8000000
#ifdef CONFIG_PHYS_64BIT
#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/*
* I2C
*/
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+#define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
#endif
/*
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
+#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
+#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
+#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC2"
-#define CONFIG_TSEC4
-#define CONFIG_TSEC4_NAME "eTSEC3"
-#undef CONFIG_MPC85XX_FEC
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#endif /* CONFIG_TSEC_ENET */
+#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
/*
* Miscellaneous configurable options
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
/*
* Environment Configuration
*/
-#define CONFIG_IPADDR 192.168.1.253
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ecc=off\0" \
"netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_TEXT_BASE) \
" +$filesize; " \
projects / platform / kernel / u-boot.git / blobdiff