Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc8349ads

[platform/kernel/u-boot.git] / include / configs / MPC8349ADS.h

diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h
index 5677fa1..1e9a1f7 100644 (file)
--- a/include/configs/MPC8349ADS.h
+++ b/include/configs/MPC8349ADS.h
@@ -149,7 +149,7 @@
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK      1
-#define CFG_INIT_RAM_ADDR      0xe4010000   /* Initial RAM address */
+#define CFG_INIT_RAM_ADDR      0x40000000   /* Initial RAM address */
 #define CFG_INIT_RAM_END       0x1000       /* End of used area in RAM*/
 
 #define CFG_GBL_DATA_SIZE      0x100     /* num bytes initial data */
@@ -512,6 +512,10 @@
        HRCWH_TSEC2M_IN_GMII )
 #endif
 
+/* System IO Config */
+#define CFG_SICRH      SICRH_TSOBI1
+#define CFG_SICRL      SICRL_LDP_A
+
 #define CFG_HID0_INIT 0x000000000
 
 #define CFG_HID0_FINAL CFG_HID0_INIT
@@ -521,7 +525,66 @@
        HID0_ENABLE_M_BIT |\
        HID0_ENABLE_ADDRESS_BROADCAST ) */
 
-#define CFG_HID2 0x000000000
+#define CFG_HID2 HID2_HBE
+
+/* DDR 0 - 256MB */
+#define CFG_IBAT0L     (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U     (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L     (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U     (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* 2G - 3G PCI */
+#ifdef CONFIG_PCI
+#define CFG_IBAT2L     (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U     (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L     (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U     (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT2L     (0)
+#define CFG_IBAT2U     (0)
+#define CFG_IBAT3L     (0)
+#define CFG_IBAT3U     (0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT4L     (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U     (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L     (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT4L     (0)
+#define CFG_IBAT4U     (0)
+#define CFG_IBAT5L     (0)
+#define CFG_IBAT5U     (0)
+#endif
+
+/* IMMRBAR */
+#define CFG_IBAT6L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U     (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM, BCSR & FLASH */
+#define CFG_IBAT7L     (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U     (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L     CFG_IBAT0L
+#define CFG_DBAT0U     CFG_IBAT0U
+#define CFG_DBAT1L     CFG_IBAT1L
+#define CFG_DBAT1U     CFG_IBAT1U
+#define CFG_DBAT2L     CFG_IBAT2L
+#define CFG_DBAT2U     CFG_IBAT2U
+#define CFG_DBAT3L     CFG_IBAT3L
+#define CFG_DBAT3U     CFG_IBAT3U
+#define CFG_DBAT4L     CFG_IBAT4L
+#define CFG_DBAT4U     CFG_IBAT4U
+#define CFG_DBAT5L     CFG_IBAT5L
+#define CFG_DBAT5U     CFG_IBAT5U
+#define CFG_DBAT6L     CFG_IBAT6L
+#define CFG_DBAT6U     CFG_IBAT6U
+#define CFG_DBAT7L     CFG_IBAT7L
+#define CFG_DBAT7U     CFG_IBAT7U
+
 
 /*
  * Internal Definitions