mpc83xx: Migrate arbiter config to Kconfig

[platform/kernel/u-boot.git] / include / configs / MPC8313ERDB_NOR.h

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 1b2bba9..608565a 100644 (file)
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -30,8 +30,6 @@
 #define CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
 
-#define CONFIG_SYS_IMMR                0xE0000000
-
 #define CONFIG_SYS_MEMTEST_START       0x00001000
 #define CONFIG_SYS_MEMTEST_END         0x07f00000
 
@@ -41,9 +39,6 @@
  */
 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
 
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
-
 /*
  * Device configurations
  */
@@ -143,17 +138,6 @@
 #define CONFIG_SYS_FLASH_PROTECTION    1       /* Use h/w Flash protection. */
 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* display empty sectors */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_9 \
-                               | OR_GPCM_EHTR \
-                               | OR_GPCM_EAD)
-                               /* 0xFF006FF7   TODO SLOW 16 MB flash size */
-
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      135     /* sectors per device */
 
@@ -199,21 +183,6 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  \
-                               (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF8396 */
-
 /* Still needed for spl_minimal.c */
 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
@@ -222,20 +191,6 @@
 #define CONFIG_SYS_BCSR_ADDR           0xFA000000
 #define CONFIG_SYS_BCSR_SIZE           (32 * 1024)     /* 0x00008000 */
                                        /* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_BCSR_ADDR \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-                                       /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFF8FF7 */
 /* Vitesse 7385 */
 
 #ifdef CONFIG_VSC7385_ENET
@@ -244,19 +199,7 @@
 #define CONFIG_SYS_VSC7385_BASE                0xF0000000
 #define CONFIG_SYS_VSC7385_SIZE                (128 * 1024)    /* 0x00020000 */
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_SETA \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFE09FF */
+
 #endif
 
 #define CONFIG_MPC83XX_GPIO 1
@@ -387,13 +330,6 @@
                        /* Enable Internal USB Phy and GPIO on LCD Connector */
 #define CONFIG_SYS_SICRL       (SICRL_USBDR_10 | SICRL_LBC)
 
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE | \
-                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
 /*
  * Environment Configuration
  */