#define CONFIG_M54451EVB /* M54451EVB board */
#define CONFIG_MCFUART
-#define CFG_UART_PORT (0)
+#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
-# define CFG_DISCOVER_PHY
-# define CFG_RX_ETH_BUFFER 8
-# define CFG_FAULT_ECHO_LINK_DOWN
+# define CONFIG_SYS_DISCOVER_PHY
+# define CONFIG_SYS_RX_ETH_BUFFER 8
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CFG_FEC0_PINMUX 0
-# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define CONFIG_SYS_FEC0_PINMUX 0
+# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
-/* If CFG_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CFG_DISCOVER_PHY
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
-# ifndef CFG_FAULT_ECHO_LINK_DOWN
-# define CFG_FAULT_ECHO_LINK_DOWN
+# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
-# endif /* CFG_DISCOVER_PHY */
+# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
#define CONFIG_HOSTNAME M54451EVB
-#ifdef CFG_STMICRO_BOOT
+#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
-#define CFG_LOAD_ADDR2 0x40010007
+#define CONFIG_SYS_LOAD_ADDR2 0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
+ "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"sbfhdr=sbfhdr.bin\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \
+ "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:1 10000 1;" \
"sf erase 0 30000;" \
"save\0" \
""
#else
-#define CFG_UBOOT_END 0x3FFFF
+#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
+ "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 " MK_STR(CFG_UBOOT_END) \
- "; era 0 " MK_STR(CFG_UBOOT_END) " ;" \
+ "prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \
+ "; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
-#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
+#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
/* Timer */
#define CONFIG_MCFTMR
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_OFFSET 0x58000
-#define CFG_IMMR CFG_MBAR
+#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
-#define CFG_SER_FLASH_BASE 0x01000000
-#define CFG_SBFHDR_SIZE 0x7
+#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
+#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
# define CONFIG_SPI_FLASH
# define CONFIG_SPI_FLASH_STMICRO
-# define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
+# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
DSPI_DCTAR_CPOL | \
DSPI_DCTAR_CPHA | \
DSPI_DCTAR_PCSSCK_1CLK | \
#define CONFIG_PRAM 2048 /* 2048 KB */
-#define CFG_PROMPT "-> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "-> "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-#define CFG_HZ 1000
+#define CONFIG_SYS_HZ 1000
-#define CFG_MBAR 0xFC000000
+#define CONFIG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR 0x80000000
-#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
-#define CFG_INIT_RAM_CTRL 0x221
-#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32)
+#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x40000000
-#define CFG_SDRAM_SIZE 128 /* SDRAM size in MB */
-#define CFG_SDRAM_CFG1 0x33633F30
-#define CFG_SDRAM_CFG2 0x57670000
-#define CFG_SDRAM_CTRL 0xE20D2C00
-#define CFG_SDRAM_EMOD 0x80810000
-#define CFG_SDRAM_MODE 0x008D0000
-#define CFG_SDRAM_DRV_STRENGTH 0x44
-
-#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
-#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
+#define CONFIG_SYS_SDRAM_CFG2 0x57670000
+#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
+#define CONFIG_SYS_SDRAM_EMOD 0x80810000
+#define CONFIG_SYS_SDRAM_MODE 0x008D0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#ifdef CONFIG_CF_SBF
-# define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
+# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
#else
-# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
-#define CFG_BOOTPARAMS_LEN 64*1024
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
# define CONFIG_ENV_SECT_SIZE 0x10000
#else
# define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
# define CONFIG_ENV_SECT_SIZE 0x2000
#endif
#undef CONFIG_ENV_OVERWRITE
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#ifdef CFG_STMICRO_BOOT
-# define CFG_FLASH_BASE CFG_SER_FLASH_BASE
-# define CFG_FLASH0_BASE CFG_SER_FLASH_BASE
-# define CFG_FLASH1_BASE CFG_CS0_BASE
+#ifdef CONFIG_SYS_STMICRO_BOOT
+# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
+# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
+# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
#endif
-#ifdef CFG_SPANSION_BOOT
-# define CFG_FLASH_BASE CFG_CS0_BASE
-# define CFG_FLASH0_BASE CFG_CS0_BASE
-# define CFG_FLASH1_BASE CFG_SER_FLASH_BASE
+#ifdef CONFIG_SYS_SPANSION_BOOT
+# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
+# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_SER_FLASH_BASE
#endif
-#define CFG_FLASH_CFI
-#ifdef CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
-# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-# define CFG_FLASH_CHECKSUM
-# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE }
+# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CONFIG_SYS_FLASH_CHECKSUM
+# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
#endif
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
-#ifdef CFG_SPANSION_BOOT
+#ifdef CONFIG_SYS_SPANSION_BOOT
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
+# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
-#ifdef CFG_STMICRO_BOOT
+#ifdef CONFIG_SYS_STMICRO_BOOT
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
+# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16
+#define CONFIG_SYS_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/* SPANSION Flash */
-#define CFG_CS0_BASE 0x00000000
-#define CFG_CS0_MASK 0x007F0001
-#define CFG_CS0_CTRL 0x00001180
+#define CONFIG_SYS_CS0_BASE 0x00000000
+#define CONFIG_SYS_CS0_MASK 0x007F0001
+#define CONFIG_SYS_CS0_CTRL 0x00001180
-#define CFG_SPANSION_BASE CFG_CS0_BASE
+#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
#endif /* _M54451EVB_H */
projects / platform / kernel / u-boot.git / blobdiff