* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
-
-#define CONFIG_WATCHDOG_TIMEOUT 5000
-
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_HAS_ETH1
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/* Timer */
-#define CONFIG_MCFTMR
+#define CFG_SYS_UART_PORT (0)
/* I2C */
-#define CONFIG_UDP_CHECKSUM
-
-#ifdef CONFIG_MCFFEC
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-#endif /* CONFIG_MCFFEC */
-
-#define CONFIG_HOSTNAME "M5208EVBe"
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"save\0" \
""
-#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
-#define CONFIG_SYS_PLL_ODR 0x36
-#define CONFIG_SYS_PLL_FDR 0x7D
+#define CFG_SYS_CLK 166666666 /* CPU Core Clock */
+#define CFG_SYS_PLL_ODR 0x36
+#define CFG_SYS_PLL_FDR 0x7D
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* You should know what you are doing if you make changes here.
*/
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x43711630
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
-#define CONFIG_SYS_SDRAM_EMOD 0x80010000
-#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
-
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x43711630
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1002000
+#define CFG_SYS_SDRAM_EMOD 0x80010000
+#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/*
* Configuration for environment
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x007F0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x007F0001
+#define CFG_SYS_CS0_CTRL 0x00001FA0
+
#endif /* _M5208EVBE_H */
projects / platform / kernel / u-boot.git / blobdiff