+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2011-12 The Chromium OS Authors.
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* This file is derived from the flashrom project.
*/
#include <dm.h>
#include <errno.h>
#include <malloc.h>
-#include <spi.h>
+#include <pch.h>
#include <pci.h>
#include <pci_ids.h>
+#include <spi.h>
#include <asm/io.h>
#include "ich.h"
-#define SPI_OPCODE_WREN 0x06
-#define SPI_OPCODE_FAST_READ 0x0b
+DECLARE_GLOBAL_DATA_PTR;
-struct ich_spi_platdata {
- pci_dev_t dev; /* PCI device number */
- int ich_version; /* Controller version, 7 or 9 */
- bool use_sbase; /* Use SBASE instead of RCB */
-};
-
-struct ich_spi_priv {
- int ichspi_lock;
- int locked;
- int opmenu;
- int menubytes;
- void *base; /* Base of register set */
- int preop;
- int optype;
- int addr;
- int data;
- unsigned databytes;
- int status;
- int control;
- int bbar;
- uint32_t *pr; /* only for ich9 */
- int speed; /* pointer to speed control */
- ulong max_speed; /* Maximum bus speed in MHz */
- ulong cur_speed; /* Current bus speed */
- struct spi_trans trans; /* current transaction in progress */
-};
+#ifdef DEBUG_TRACE
+#define debug_trace(fmt, args...) debug(fmt, ##args)
+#else
+#define debug_trace(x, args...)
+#endif
static u8 ich_readb(struct ich_spi_priv *priv, int reg)
{
u8 value = readb(priv->base + reg);
- debug("read %2.2x from %4.4x\n", value, reg);
+ debug_trace("read %2.2x from %4.4x\n", value, reg);
return value;
}
{
u16 value = readw(priv->base + reg);
- debug("read %4.4x from %4.4x\n", value, reg);
+ debug_trace("read %4.4x from %4.4x\n", value, reg);
return value;
}
{
u32 value = readl(priv->base + reg);
- debug("read %8.8x from %4.4x\n", value, reg);
+ debug_trace("read %8.8x from %4.4x\n", value, reg);
return value;
}
static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
{
writeb(value, priv->base + reg);
- debug("wrote %2.2x to %4.4x\n", value, reg);
+ debug_trace("wrote %2.2x to %4.4x\n", value, reg);
}
static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
{
writew(value, priv->base + reg);
- debug("wrote %4.4x to %4.4x\n", value, reg);
+ debug_trace("wrote %4.4x to %4.4x\n", value, reg);
}
static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
{
writel(value, priv->base + reg);
- debug("wrote %8.8x to %4.4x\n", value, reg);
+ debug_trace("wrote %8.8x to %4.4x\n", value, reg);
}
static void write_reg(struct ich_spi_priv *priv, const void *value,
ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
}
-/*
- * Check if this device ID matches one of supported Intel PCH devices.
- *
- * Return the ICH version if there is a match, or zero otherwise.
- */
-static int get_ich_version(uint16_t device_id)
-{
- if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
- device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
- device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
- return 7;
-
- if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
- device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
- (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
- device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
- device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
- device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC)
- return 9;
-
- return 0;
-}
-
/* @return 1 if the SPI flash supports the 33MHz speed */
-static int ich9_can_do_33mhz(pci_dev_t dev)
+static int ich9_can_do_33mhz(struct udevice *dev)
{
u32 fdod, speed;
/* Observe SPI Descriptor Component Section 0 */
- pci_write_config_dword(dev, 0xb0, 0x1000);
+ dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
/* Extract the Write/Erase SPI Frequency from descriptor */
- pci_read_config_dword(dev, 0xb4, &fdod);
+ dm_pci_read_config32(dev->parent, 0xb4, &fdod);
/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
speed = (fdod >> 21) & 7;
return speed == 1;
}
-static int ich_find_spi_controller(struct ich_spi_platdata *ich)
-{
- int last_bus = pci_last_busno();
- int bus;
-
- if (last_bus == -1) {
- debug("No PCI busses?\n");
- return -ENODEV;
- }
-
- for (bus = 0; bus <= last_bus; bus++) {
- uint16_t vendor_id, device_id;
- uint32_t ids;
- pci_dev_t dev;
-
- dev = PCI_BDF(bus, 31, 0);
- pci_read_config_dword(dev, 0, &ids);
- vendor_id = ids;
- device_id = ids >> 16;
-
- if (vendor_id == PCI_VENDOR_ID_INTEL) {
- ich->dev = dev;
- ich->ich_version = get_ich_version(device_id);
- if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
- ich->use_sbase = true;
- return ich->ich_version == 0 ? -ENODEV : 0;
- }
- }
-
- debug("ICH SPI: No ICH found.\n");
- return -ENODEV;
-}
-
-static int ich_init_controller(struct ich_spi_platdata *plat,
+static int ich_init_controller(struct udevice *dev,
+ struct ich_spi_platdata *plat,
struct ich_spi_priv *ctlr)
{
- uint8_t *rcrb; /* Root Complex Register Block */
- uint32_t rcba; /* Root Complex Base Address */
- uint32_t sbase_addr;
- uint8_t *sbase;
-
- pci_read_config_dword(plat->dev, 0xf0, &rcba);
- /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
- rcrb = (uint8_t *)(rcba & 0xffffc000);
+ ulong sbase_addr;
+ void *sbase;
/* SBASE is similar */
- pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
- sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
+ pch_get_spi_base(dev->parent, &sbase_addr);
+ sbase = (void *)sbase_addr;
+ debug("%s: sbase=%p\n", __func__, sbase);
- if (plat->ich_version == 7) {
- struct ich7_spi_regs *ich7_spi;
+ if (plat->ich_version == ICHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
- ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
- ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich7_spi->opmenu);
ctlr->optype = offsetof(struct ich7_spi_regs, optype);
ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
ctlr->preop = offsetof(struct ich7_spi_regs, preop);
ctlr->base = ich7_spi;
- } else if (plat->ich_version == 9) {
- struct ich9_spi_regs *ich9_spi;
+ } else if (plat->ich_version == ICHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
- if (plat->use_sbase)
- ich9_spi = (struct ich9_spi_regs *)sbase;
- else
- ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
- ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich9_spi->opmenu);
ctlr->optype = offsetof(struct ich9_spi_regs, optype);
ctlr->speed = ctlr->control + 2;
ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
ctlr->preop = offsetof(struct ich9_spi_regs, preop);
+ ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
ctlr->pr = &ich9_spi->pr[0];
ctlr->base = ich9_spi;
} else {
/* Work out the maximum speed we can support */
ctlr->max_speed = 20000000;
- if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
+ if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
ctlr->max_speed = 33000000;
- debug("ICH SPI: Version %d detected at %p, speed %ld\n",
+ debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
plat->ich_version, ctlr->base, ctlr->max_speed);
ich_set_bbar(ctlr, 0);
trans->bytesin -= bytes;
}
+static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
+{
+ if (plat->ich_version == ICHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
+
+ setbits_le16(&ich7_spi->spis, SPIS_LOCK);
+ } else if (plat->ich_version == ICHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
+
+ setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
+ }
+}
+
+static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
+{
+ int lock = 0;
+
+ if (plat->ich_version == ICHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
+
+ lock = readw(&ich7_spi->spis) & SPIS_LOCK;
+ } else if (plat->ich_version == ICHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
+
+ lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ }
+
+ return lock != 0;
+}
+
static void spi_setup_type(struct spi_trans *trans, int data_bytes)
{
trans->type = 0xFF;
- /* Try to guess spi type from read/write sizes. */
+ /* Try to guess spi type from read/write sizes */
if (trans->bytesin == 0) {
if (trans->bytesout + data_bytes > 4)
/*
}
}
-static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
+static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
+ bool lock)
{
uint16_t optypes;
uint8_t opmenu[ctlr->menubytes];
trans->opcode = trans->out[0];
spi_use_out(trans, 1);
- if (!ctlr->ichspi_lock) {
+ if (!lock) {
/* The lock is off, so just use index 0. */
ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
optypes = ich_readw(ctlr, ctlr->optype);
static int spi_setup_offset(struct spi_trans *trans)
{
- /* Separate the SPI address and data. */
+ /* Separate the SPI address and data */
switch (trans->type) {
case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
return -ETIMEDOUT;
}
+void ich_spi_config_opcode(struct udevice *dev)
+{
+ struct ich_spi_priv *ctlr = dev_get_priv(dev);
+
+ /*
+ * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
+ * to prevent accidental or intentional writes. Before they get
+ * locked down, these registers should be initialized properly.
+ */
+ ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
+ ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
+ ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
+ ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
+}
+
static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
+ struct ich_spi_platdata *plat = dev_get_platdata(bus);
struct ich_spi_priv *ctlr = dev_get_priv(bus);
uint16_t control;
int16_t opcode_index;
struct spi_trans *trans = &ctlr->trans;
unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
int using_cmd = 0;
+ bool lock = spi_lock_status(plat, ctlr->base);
int ret;
- /* Ee don't support writing partial bytes. */
+ /* We don't support writing partial bytes */
if (bitlen % 8) {
debug("ICH SPI: Accessing partial bytes not supported\n");
return -EPROTONOSUPPORT;
}
memcpy(trans->cmd, dout, bytes);
trans->cmd_len = bytes;
- debug("ICH SPI: Saved %d bytes\n", bytes);
+ debug_trace("ICH SPI: Saved %d bytes\n", bytes);
return 0;
}
trans->out = trans->cmd;
trans->bytesout = trans->cmd_len;
using_cmd = 1;
- debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
+ debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
} else {
trans->out = dout;
trans->bytesout = dout ? bytes : 0;
trans->in = din;
trans->bytesin = din ? bytes : 0;
- /* There has to always at least be an opcode. */
+ /* There has to always at least be an opcode */
if (!trans->bytesout) {
debug("ICH SPI: No opcode for transfer\n");
return -EPROTO;
if (ret < 0)
return ret;
- ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+ if (plat->ich_version == ICHV_7)
+ ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+ else
+ ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
spi_setup_type(trans, using_cmd ? bytes : 0);
- opcode_index = spi_setup_opcode(ctlr, trans);
+ opcode_index = spi_setup_opcode(ctlr, trans, lock);
if (opcode_index < 0)
return -EINVAL;
with_address = spi_setup_offset(trans);
* in order to prevent the Management Engine from
* issuing a transaction between WREN and DATA.
*/
- if (!ctlr->ichspi_lock)
+ if (!lock)
ich_writew(ctlr, trans->opcode, ctlr->preop);
return 0;
}
if (using_cmd && dout && bytes) {
trans->out = dout;
trans->bytesout = bytes;
- debug("ICH SPI: Moving to data, %d bytes\n", bytes);
+ debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
}
/* Preset control fields */
- control = ich_readw(ctlr, ctlr->control);
- control &= ~SSFC_RESERVED;
control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
/* Issue atomic preop cycle if needed */
/* write it */
ich_writew(ctlr, control, ctlr->control);
- /* Wait for Cycle Done Status or Flash Cycle Error. */
+ /* Wait for Cycle Done Status or Flash Cycle Error */
status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
if (status < 0)
return status;
if (status & SPIS_FCERR) {
- debug("ICH SPI: Data transaction error\n");
+ debug("ICH SPI: Data transaction error %x\n", status);
return -EIO;
}
}
/* Clear atomic preop now that xfer is done */
- ich_writew(ctlr, 0, ctlr->preop);
+ if (!lock)
+ ich_writew(ctlr, 0, ctlr->preop);
return 0;
}
-
-/*
- * This uses the SPI controller from the Intel Cougar Point and Panther Point
- * PCH to write-protect portions of the SPI flash until reboot. The changes
- * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
- * done elsewhere.
- */
-int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
- uint32_t length, int hint)
+static int ich_spi_probe(struct udevice *dev)
{
- struct udevice *bus = dev->parent;
- struct ich_spi_priv *ctlr = dev_get_priv(bus);
- uint32_t tmplong;
- uint32_t upper_limit;
-
- if (!ctlr->pr) {
- printf("%s: operation not supported on this chipset\n",
- __func__);
- return -ENOSYS;
- }
-
- if (length == 0 ||
- lower_limit > (0xFFFFFFFFUL - length) + 1 ||
- hint < 0 || hint > 4) {
- printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
- lower_limit, length, hint);
- return -EPERM;
- }
-
- upper_limit = lower_limit + length - 1;
-
- /*
- * Determine bits to write, as follows:
- * 31 Write-protection enable (includes erase operation)
- * 30:29 reserved
- * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
- * 15 Read-protection enable
- * 14:13 reserved
- * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
- */
- tmplong = 0x80000000 |
- ((upper_limit & 0x01fff000) << 4) |
- ((lower_limit & 0x01fff000) >> 12);
-
- printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
- &ctlr->pr[hint]);
- ctlr->pr[hint] = tmplong;
-
- return 0;
-}
-
-static int ich_spi_probe(struct udevice *bus)
-{
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
- struct ich_spi_priv *priv = dev_get_priv(bus);
+ struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ struct ich_spi_priv *priv = dev_get_priv(dev);
uint8_t bios_cntl;
int ret;
- ret = ich_init_controller(plat, priv);
+ ret = ich_init_controller(dev, plat, priv);
if (ret)
return ret;
- /*
- * Disable the BIOS write protect so write commands are allowed. On
- * v9, deassert SMM BIOS Write Protect Disable.
- */
- if (plat->use_sbase) {
- struct ich9_spi_regs *ich9_spi;
-
- ich9_spi = priv->base;
- bios_cntl = ich_readb(priv, ich9_spi->bcr);
- bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
+ /* Disable the BIOS write protect so write commands are allowed */
+ ret = pch_set_spi_protect(dev->parent, false);
+ if (ret == -ENOSYS) {
+ bios_cntl = ich_readb(priv, priv->bcr);
+ bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
bios_cntl |= 1; /* Write Protect Disable (WPD) */
- ich_writeb(priv, bios_cntl, ich9_spi->bcr);
- } else {
- pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
- if (plat->ich_version == 9)
- bios_cntl &= ~(1 << 5);
- pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
+ ich_writeb(priv, bios_cntl, priv->bcr);
+ } else if (ret) {
+ debug("%s: Failed to disable write-protect: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* Lock down SPI controller settings if required */
+ if (plat->lockdown) {
+ ich_spi_config_opcode(dev);
+ spi_lock_down(plat, priv->base);
}
priv->cur_speed = priv->max_speed;
return 0;
}
-static int ich_spi_ofdata_to_platdata(struct udevice *bus)
+static int ich_spi_remove(struct udevice *bus)
{
- struct ich_spi_platdata *plat = dev_get_platdata(bus);
- int ret;
-
- ret = ich_find_spi_controller(plat);
- if (ret)
- return ret;
+ /*
+ * Configure SPI controller so that the Linux MTD driver can fully
+ * access the SPI NOR chip
+ */
+ ich_spi_config_opcode(bus);
return 0;
}
struct udevice *bus = dev_get_parent(dev);
struct ich_spi_platdata *plat = dev_get_platdata(bus);
struct ich_spi_priv *priv = dev_get_priv(bus);
- struct spi_slave *slave = dev_get_parentdata(dev);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
/*
* Yes this controller can only write a small number of bytes at
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
*/
- if (plat->ich_version == 7) {
- slave->op_mode_rx = SPI_OPM_RX_AS;
- slave->op_mode_tx = SPI_OPM_TX_BP;
- }
+ if (plat->ich_version == ICHV_7)
+ slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
return 0;
}
+static int ich_spi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ int node = dev_of_offset(dev);
+ int ret;
+
+ ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi");
+ if (ret == 0) {
+ plat->ich_version = ICHV_7;
+ } else {
+ ret = fdt_node_check_compatible(gd->fdt_blob, node,
+ "intel,ich9-spi");
+ if (ret == 0)
+ plat->ich_version = ICHV_9;
+ }
+
+ plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node,
+ "intel,spi-lock-down");
+
+ return ret;
+}
+
static const struct dm_spi_ops ich_spi_ops = {
.xfer = ich_spi_xfer,
.set_speed = ich_spi_set_speed,
};
static const struct udevice_id ich_spi_ids[] = {
- { .compatible = "intel,ich-spi" },
+ { .compatible = "intel,ich7-spi" },
+ { .compatible = "intel,ich9-spi" },
{ }
};
.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
.child_pre_probe = ich_spi_child_pre_probe,
.probe = ich_spi_probe,
+ .remove = ich_spi_remove,
+ .flags = DM_FLAG_OS_PREPARE,
};
projects / platform / kernel / u-boot.git / blobdiff