SPDX: Convert all of our single license tags to Linux Kernel style

[platform/kernel/u-boot.git] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 2085cd6..375b854 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -49,8 +48,13 @@ static void set_inbound_window(volatile pit_t *pi,
                                u64 size)
 {
        u32 sz = (__ilog2_u64(size) - 1);
-       u32 flag = PIWAR_EN | PIWAR_LOCAL |
-                       PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+       u32 flag = 0;
+#else
+       u32 flag = PIWAR_LOCAL;
+#endif
+
+       flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
 
        out_be32(&pi->pitar, r->phys_start >> 12);
        out_be32(&pi->piwbar, r->bus_start >> 12);
@@ -385,7 +389,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        /* boot from PCIE --master */
-       char *s = getenv("bootmaster");
+       char *s = env_get("bootmaster");
        char pcie[6];
        sprintf(pcie, "PCIE%d", pci_info->pci_num);
 
@@ -439,6 +443,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
                        ltssm = (in_be32(&pci->pex_csr0)
                                & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
                        enabled = (ltssm == 0x11) ? 1 : 0;
+#ifdef CONFIG_FSL_PCIE_RESET
+                       int i;
+                       /* assert PCIe reset */
+                       setbits_be32(&pci->pdb_stat, 0x08000000);
+                       (void) in_be32(&pci->pdb_stat);
+                       udelay(1000);
+                       /* clear PCIe reset */
+                       clrbits_be32(&pci->pdb_stat, 0x08000000);
+                       asm("sync;isync");
+                       for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
+                               pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+                                                         &ltssm);
+                               udelay(1000);
+                       }
+#endif
                } else {
                /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
                /* enabled = ltssm >= PCI_LTSSM_L0; */
@@ -499,8 +518,14 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
                }
 #endif
                if (!enabled) {
-                       /* Let the user know there's no PCIe link */
-                       printf("no link, regs @ 0x%lx\n", pci_info->regs);
+                       /* Let the user know there's no PCIe link for root
+                        * complex. for endpoint, the link may not setup, so
+                        * print undetermined.
+                        */
+                       if (fsl_is_pci_agent(hose))
+                               printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
+                       else
+                               printf("no link, regs @ 0x%lx\n", pci_info->regs);
                        hose->last_busno = hose->first_busno;
                        return;
                }
@@ -510,13 +535,20 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 
                /* Print the negotiated PCIe link width */
                pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
-               printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
-                       pci_info->regs);
+               printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
+                      (temp16 & 0xf), pci_info->regs);
 
                hose->current_busno++; /* Start scan with secondary */
                pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
        }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+       /* The Read-Only Write Enable bit defaults to 1 instead of 0.
+        * Set to 0 to protect the read-only registers.
+        */
+       clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
+#endif
+
        /* Use generic setup_device to initialize standard pci regs,
         * but do not allocate any windows since any BAR found (such
         * as PCSRBAR) is not in this cpu's memory space.
@@ -640,7 +672,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        } else {
                /* boot from PCIE --master releases slave's core 0 */
-               char *s = getenv("bootmaster");
+               char *s = env_get("bootmaster");
                char pcie[6];
                sprintf(pcie, "PCIE%d", pci_info->pci_num);
 
@@ -671,8 +703,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
        pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
        pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
        if (pcie_cap != 0x0) {
+               ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
+               u32 block_rev = in_be32(&pci->block_rev1);
                /* PCIe - set CFG_READY bit of Configuration Ready Register */
-               pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+               if (block_rev >= PEX_IP_BLK_REV_3_0)
+                       setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
+               else
+                       pci_hose_write_config_byte(hose, dev,
+                                                  FSL_PCIE_CFG_RDY, 0x1);
        } else {
                /* PCI - clear ACL bit of PBFR */
                pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
@@ -847,7 +885,7 @@ int fsl_pcie_init_board(int busno)
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
+#include <linux/libfdt.h>
 #include <fdt_support.h>
 
 void ft_fsl_pci_setup(void *blob, const char *pci_compat,