+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Andy Fleming
* Based vaguely on the pxa mmc code:
* (C) Copyright 2003
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
+#include <power/regulator.h>
#include <malloc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <dm.h>
#include <asm-generic/gpio.h>
+#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
IRQSTATEN_DINT)
+#define MAX_TUNING_LOOP 40
struct fsl_esdhc {
uint dsaddr; /* SDMA system address register */
uint dllctrl;
uint dllstat;
uint clktunectrlstatus;
- char reserved3[84];
+ char reserved3[4];
+ uint strobe_dllctrl;
+ uint strobe_dllstat;
+ char reserved4[72];
uint vendorspec;
uint mmcboot;
uint vendorspec2;
- char reserved4[48];
+ uint tuning_ctrl; /* on i.MX6/7/8 */
+ char reserved5[44];
uint hostver; /* Host controller version register */
- char reserved5[4]; /* reserved */
- uint dmaerraddr; /* DMA error address register */
char reserved6[4]; /* reserved */
- uint dmaerrattr; /* DMA error attribute register */
+ uint dmaerraddr; /* DMA error address register */
char reserved7[4]; /* reserved */
+ uint dmaerrattr; /* DMA error attribute register */
+ char reserved8[4]; /* reserved */
uint hostcapblt2; /* Host controller capabilities register 2 */
- char reserved8[8]; /* reserved */
+ char reserved9[8]; /* reserved */
uint tcr; /* Tuning control register */
- char reserved9[28]; /* reserved */
+ char reserved10[28]; /* reserved */
uint sddirctl; /* SD direction control register */
- char reserved10[712];/* reserved */
+ char reserved11[712];/* reserved */
uint scr; /* eSDHC control register */
};
+struct fsl_esdhc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct esdhc_soc_data {
+ u32 flags;
+ u32 caps;
+};
+
/**
* struct fsl_esdhc_priv
*
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
+ * @caps: controller capabilities
+ * @tuning_step: tuning step setting in tuning_ctrl register
+ * @start_tuning_tap: the start point for tuning in tuning_ctrl register
+ * @strobe_dll_delay_target: settings in strobe_dllctrl
+ * @signal_voltage: indicating the current voltage
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
+ unsigned int clock;
+ unsigned int mode;
unsigned int bus_width;
- struct mmc_config cfg;
+#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
+#endif
struct udevice *dev;
int non_removable;
int wp_enable;
+ int vs18_enable;
+ u32 flags;
+ u32 caps;
+ u32 tuning_step;
+ u32 tuning_start_tap;
+ u32 strobe_dll_delay_target;
+ u32 signal_voltage;
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+ struct udevice *vqmmc_dev;
+ struct udevice *vmmc_dev;
+#endif
#ifdef CONFIG_DM_GPIO
struct gpio_desc cd_gpio;
struct gpio_desc wp_gpio;
/*
* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
*/
-static void
-esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
+ struct mmc_data *data)
{
- struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
uint blocks;
char *buffer;
uint databuf;
uint size;
uint irqstat;
- uint timeout;
+ ulong start;
if (data->flags & MMC_DATA_READ) {
blocks = data->blocks;
buffer = data->dest;
while (blocks) {
- timeout = PIO_TIMEOUT;
+ start = get_timer(0);
size = data->blocksize;
irqstat = esdhc_read32(®s->irqstat);
- while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
- && --timeout);
- if (timeout <= 0) {
- printf("\nData Read Failed in PIO Mode.");
- return;
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
+ if (get_timer(start) > PIO_TIMEOUT) {
+ printf("\nData Read Failed in PIO Mode.");
+ return;
+ }
}
while (size && (!(irqstat & IRQSTAT_TC))) {
udelay(100); /* Wait before last byte transfer complete */
blocks = data->blocks;
buffer = (char *)data->src;
while (blocks) {
- timeout = PIO_TIMEOUT;
+ start = get_timer(0);
size = data->blocksize;
irqstat = esdhc_read32(®s->irqstat);
- while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
- && --timeout);
- if (timeout <= 0) {
- printf("\nData Write Failed in PIO Mode.");
- return;
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
+ if (get_timer(start) > PIO_TIMEOUT) {
+ printf("\nData Write Failed in PIO Mode.");
+ return;
+ }
}
while (size && (!(irqstat & IRQSTAT_TC))) {
udelay(100); /* Wait before last byte transfer complete */
}
#endif
-static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
+static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ struct mmc_data *data)
{
int timeout;
- struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
dma_addr_t addr;
#endif
uint wml_value;
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+ defined(CONFIG_MX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
*/
-static int
-esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ struct mmc_cmd *cmd, struct mmc_data *data)
{
int err = 0;
uint xfertyp;
uint irqstat;
- struct fsl_esdhc_priv *priv = mmc->priv;
+ u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
struct fsl_esdhc *regs = priv->esdhc_regs;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
/* Set up for a data transfer if we have one */
if (data) {
- err = esdhc_setup_data(mmc, data);
+ err = esdhc_setup_data(priv, mmc, data);
if(err)
return err;
esdhc_write32(®s->xfertyp, xfertyp);
#endif
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
+ flags = IRQSTAT_BRR;
+
/* Wait for the command to complete */
- while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
+ while (!(esdhc_read32(®s->irqstat) & flags))
;
irqstat = esdhc_read32(®s->irqstat);
/* Wait until all of the blocks are transferred */
if (data) {
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
- esdhc_pio_read_write(mmc, data);
+ esdhc_pio_read_write(priv, data);
#else
+ flags = DATA_COMPLETE;
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
+ flags = IRQSTAT_BRR;
+ }
+
do {
irqstat = esdhc_read32(®s->irqstat);
err = -ECOMM;
goto out;
}
- } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
+ } while ((irqstat & flags) != flags);
/*
* Need invalidate the dcache here again to avoid any
return err;
}
-static void set_sysctl(struct mmc *mmc, uint clock)
+static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
{
- int div, pre_div;
- struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
+ int div = 1;
+#ifdef ARCH_MXC
+#ifdef CONFIG_MX53
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+#else
+ int pre_div = 1;
+#endif
+#else
+ int pre_div = 2;
+#endif
+ int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
int sdhc_clk = priv->sdhc_clk;
uint clk;
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
- if (sdhc_clk / 16 > clock) {
- for (pre_div = 2; pre_div < 256; pre_div *= 2)
- if ((sdhc_clk / pre_div) <= (clock * 16))
- break;
- } else
- pre_div = 2;
+ while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
+ pre_div *= 2;
- for (div = 1; div <= 16; div++)
- if ((sdhc_clk / (div * pre_div)) <= clock)
- break;
+ while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
+ div++;
- pre_div >>= mmc->ddr_mode ? 2 : 1;
+ pre_div >>= 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
+ priv->clock = clock;
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-static void esdhc_clock_control(struct mmc *mmc, bool enable)
+static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
{
- struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 value;
u32 time_out;
}
#endif
-static int esdhc_set_ios(struct mmc *mmc)
+#ifdef MMC_SUPPORTS_TUNING
+static int esdhc_change_pinstate(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ switch (priv->mode) {
+ case UHS_SDR50:
+ case UHS_DDR50:
+ ret = pinctrl_select_state(dev, "state_100mhz");
+ break;
+ case UHS_SDR104:
+ case MMC_HS_200:
+ ret = pinctrl_select_state(dev, "state_200mhz");
+ break;
+ default:
+ ret = pinctrl_select_state(dev, "default");
+ break;
+ }
+
+ if (ret)
+ printf("%s %d error\n", __func__, priv->mode);
+
+ return ret;
+}
+
+static void esdhc_reset_tuning(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ esdhc_clrbits32(®s->autoc12err,
+ MIX_CTRL_SMPCLK_SEL |
+ MIX_CTRL_EXE_TUNE);
+ }
+ }
+}
+
+static int esdhc_set_timing(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 mixctrl;
+
+ mixctrl = readl(®s->mixctrl);
+ mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
+
+ switch (mmc->selected_mode) {
+ case MMC_LEGACY:
+ case SD_LEGACY:
+ esdhc_reset_tuning(mmc);
+ break;
+ case MMC_HS:
+ case MMC_HS_52:
+ case MMC_HS_200:
+ case SD_HS:
+ case UHS_SDR12:
+ case UHS_SDR25:
+ case UHS_SDR50:
+ case UHS_SDR104:
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ case UHS_DDR50:
+ case MMC_DDR_52:
+ mixctrl |= MIX_CTRL_DDREN;
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ default:
+ printf("Not supported %d\n", mmc->selected_mode);
+ return -EINVAL;
+ }
+
+ priv->mode = mmc->selected_mode;
+
+ return esdhc_change_pinstate(mmc->dev);
+}
+
+static int esdhc_set_voltage(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret;
+
+ priv->signal_voltage = mmc->signal_voltage;
+ switch (mmc->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ if (priv->vs18_enable)
+ return -EIO;
+#ifdef CONFIG_DM_REGULATOR
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+ ret = regulator_set_value(priv->vqmmc_dev, 3300000);
+ if (ret) {
+ printf("Setting to 3.3V error");
+ return -EIO;
+ }
+ /* Wait for 5ms */
+ mdelay(5);
+ }
+#endif
+
+ esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ if (!(esdhc_read32(®s->vendorspec) &
+ ESDHC_VENDORSPEC_VSELECT))
+ return 0;
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_180:
+#ifdef CONFIG_DM_REGULATOR
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+ ret = regulator_set_value(priv->vqmmc_dev, 1800000);
+ if (ret) {
+ printf("Setting to 1.8V error");
+ return -EIO;
+ }
+ }
+#endif
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
+ return 0;
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_120:
+ return -ENOTSUPP;
+ default:
+ return 0;
+ }
+}
+
+static void esdhc_stop_tuning(struct mmc *mmc)
+{
+ struct mmc_cmd cmd;
+
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
+}
+
+static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ struct mmc *mmc = &plat->mmc;
+ u32 irqstaten = readl(®s->irqstaten);
+ u32 irqsigen = readl(®s->irqsigen);
+ int i, ret = -ETIMEDOUT;
+ u32 val, mixctrl;
+
+ /* clock tuning is not needed for upto 52MHz */
+ if (mmc->clock <= 52000000)
+ return 0;
+
+ /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ val = readl(®s->autoc12err);
+ mixctrl = readl(®s->mixctrl);
+ val &= ~MIX_CTRL_SMPCLK_SEL;
+ mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
+
+ val |= MIX_CTRL_EXE_TUNE;
+ mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
+
+ writel(val, ®s->autoc12err);
+ writel(mixctrl, ®s->mixctrl);
+ }
+
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
+ mixctrl = readl(®s->mixctrl);
+ mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
+ writel(mixctrl, ®s->mixctrl);
+
+ writel(IRQSTATEN_BRR, ®s->irqstaten);
+ writel(IRQSTATEN_BRR, ®s->irqsigen);
+
+ /*
+ * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
+ * of loops reaches 40 times.
+ */
+ for (i = 0; i < MAX_TUNING_LOOP; i++) {
+ u32 ctrl;
+
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
+ if (mmc->bus_width == 8)
+ writel(0x7080, ®s->blkattr);
+ else if (mmc->bus_width == 4)
+ writel(0x7040, ®s->blkattr);
+ } else {
+ writel(0x7040, ®s->blkattr);
+ }
+
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
+ val = readl(®s->mixctrl);
+ val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
+ writel(val, ®s->mixctrl);
+
+ /* We are using STD tuning, no need to check return value */
+ mmc_send_tuning(mmc, opcode, NULL);
+
+ ctrl = readl(®s->autoc12err);
+ if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
+ (ctrl & MIX_CTRL_SMPCLK_SEL)) {
+ /*
+ * need to wait some time, make sure sd/mmc fininsh
+ * send out tuning data, otherwise, the sd/mmc can't
+ * response to any command when the card still out
+ * put the tuning data.
+ */
+ mdelay(1);
+ ret = 0;
+ break;
+ }
+
+ /* Add 1ms delay for SD and eMMC */
+ mdelay(1);
+ }
+
+ writel(irqstaten, ®s->irqstaten);
+ writel(irqsigen, ®s->irqsigen);
+
+ esdhc_stop_tuning(mmc);
+
+ return ret;
+}
+#endif
+
+static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
{
- struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret __maybe_unused;
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
/* Select to use peripheral clock */
- esdhc_clock_control(mmc, false);
+ esdhc_clock_control(priv, false);
esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
- esdhc_clock_control(mmc, true);
+ esdhc_clock_control(priv, true);
#endif
/* Set the clock speed */
- set_sysctl(mmc, mmc->clock);
+ if (priv->clock != mmc->clock)
+ set_sysctl(priv, mmc, mmc->clock);
+
+#ifdef MMC_SUPPORTS_TUNING
+ if (mmc->clk_disable) {
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
+#else
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+#endif
+ } else {
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
+ VENDORSPEC_CKEN);
+#else
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+ }
+
+ if (priv->mode != mmc->selected_mode) {
+ ret = esdhc_set_timing(mmc);
+ if (ret) {
+ printf("esdhc_set_timing error %d\n", ret);
+ return ret;
+ }
+ }
+
+ if (priv->signal_voltage != mmc->signal_voltage) {
+ ret = esdhc_set_voltage(mmc);
+ if (ret) {
+ printf("esdhc_set_voltage error %d\n", ret);
+ return ret;
+ }
+ }
+#endif
/* Set the bus width */
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
return 0;
}
-static int esdhc_init(struct mmc *mmc)
+static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
{
- struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
- int timeout = 1000;
+ ulong start;
/* Reset the entire host controller */
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
/* Wait until the controller is available */
- while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
- udelay(1000);
+ start = get_timer(0);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
+ if (get_timer(start) > 1000)
+ return -ETIMEDOUT;
+ }
#if defined(CONFIG_FSL_USDHC)
/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
esdhc_write32(®s->clktunectrlstatus, 0x0);
/* Put VEND_SPEC to default value */
- esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
+ if (priv->vs18_enable)
+ esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
+ ESDHC_VENDORSPEC_VSELECT));
+ else
+ esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
/* Disable DLL_CTRL delay line */
esdhc_write32(®s->dllctrl, 0x0);
#endif
/* Set the initial clock speed */
- mmc_set_clock(mmc, 400000);
+ mmc_set_clock(mmc, 400000, false);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
-#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-#endif
-
return 0;
}
-static int esdhc_getcd(struct mmc *mmc)
+static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
{
- struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
int timeout = 1000;
return 1;
#endif
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
if (priv->non_removable)
return 1;
#ifdef CONFIG_DM_GPIO
return timeout > 0;
}
-static void esdhc_reset(struct fsl_esdhc *regs)
+static int esdhc_reset(struct fsl_esdhc *regs)
{
- unsigned long timeout = 100; /* wait max 100 ms */
+ ulong start;
/* reset the controller */
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
/* hardware clears the bit when it is done */
- while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
- udelay(1000);
- if (!timeout)
- printf("MMC/SD: Reset never completed.\n");
+ start = get_timer(0);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
+ if (get_timer(start) > 100) {
+ printf("MMC/SD: Reset never completed.\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
}
-static const struct mmc_ops esdhc_ops = {
- .send_cmd = esdhc_send_cmd,
- .set_ios = esdhc_set_ios,
- .init = esdhc_init,
- .getcd = esdhc_getcd,
-};
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int esdhc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
-static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
- struct fsl_esdhc_priv *priv)
+ return esdhc_getcd_common(priv);
+}
+
+static int esdhc_init(struct mmc *mmc)
{
- if (!cfg || !priv)
- return -EINVAL;
+ struct fsl_esdhc_priv *priv = mmc->priv;
- priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
- priv->bus_width = cfg->max_bus_width;
- priv->sdhc_clk = cfg->sdhc_clk;
- priv->wp_enable = cfg->wp_enable;
+ return esdhc_init_common(priv, mmc);
+}
- return 0;
+static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int esdhc_set_ios(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_set_ios_common(priv, mmc);
+}
+
+static const struct mmc_ops esdhc_ops = {
+ .getcd = esdhc_getcd,
+ .init = esdhc_init,
+ .send_cmd = esdhc_send_cmd,
+ .set_ios = esdhc_set_ios,
};
+#endif
-static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
+ struct fsl_esdhc_plat *plat)
{
+ struct mmc_config *cfg;
struct fsl_esdhc *regs;
- struct mmc *mmc;
u32 caps, voltage_caps;
+ int ret;
if (!priv)
return -EINVAL;
regs = priv->esdhc_regs;
/* First reset the eSDHC controller */
- esdhc_reset(regs);
+ ret = esdhc_reset(regs);
+ if (ret)
+ return ret;
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
+ /* Clearing tuning bits in case ROM has set it already */
+ esdhc_write32(®s->mixctrl, 0);
+ esdhc_write32(®s->autoc12err, 0);
+ esdhc_write32(®s->clktunectrlstatus, 0);
#else
esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
#endif
+ if (priv->vs18_enable)
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
- memset(&priv->cfg, 0, sizeof(priv->cfg));
+ cfg = &plat->cfg;
+#ifndef CONFIG_DM_MMC
+ memset(cfg, '\0', sizeof(*cfg));
+#endif
voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
if (caps & ESDHC_HOSTCAPBLT_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
- priv->cfg.name = "FSL_SDHC";
- priv->cfg.ops = &esdhc_ops;
+ cfg->name = "FSL_SDHC";
+#if !CONFIG_IS_ENABLED(DM_MMC)
+ cfg->ops = &esdhc_ops;
+#endif
#ifdef CONFIG_SYS_SD_VOLTAGE
- priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
+ cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
#else
- priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
- if ((priv->cfg.voltages & voltage_caps) == 0) {
+ if ((cfg->voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
return -1;
}
if (priv->bus_width == 8)
- priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
else if (priv->bus_width == 4)
- priv->cfg.host_caps = MMC_MODE_4BIT;
+ cfg->host_caps = MMC_MODE_4BIT;
- priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
- priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+ cfg->host_caps |= MMC_MODE_DDR_52MHz;
#endif
if (priv->bus_width > 0) {
if (priv->bus_width < 8)
- priv->cfg.host_caps &= ~MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
if (priv->bus_width < 4)
- priv->cfg.host_caps &= ~MMC_MODE_4BIT;
+ cfg->host_caps &= ~MMC_MODE_4BIT;
}
if (caps & ESDHC_HOSTCAPBLT_HSS)
- priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
- priv->cfg.host_caps &= ~MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
#endif
- priv->cfg.f_min = 400000;
- priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
+ cfg->host_caps |= priv->caps;
- priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ cfg->f_min = 400000;
+ cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
- mmc = mmc_create(&priv->cfg, priv);
- if (mmc == NULL)
- return -1;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- priv->mmc = mmc;
+ writel(0, ®s->dllctrl);
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ u32 val = readl(®s->tuning_ctrl);
+
+ val |= ESDHC_STD_TUNING_EN;
+ val &= ~ESDHC_TUNING_START_TAP_MASK;
+ val |= priv->tuning_start_tap;
+ val &= ~ESDHC_TUNING_STEP_MASK;
+ val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+ writel(val, ®s->tuning_ctrl);
+ }
+ }
return 0;
}
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+ priv->wp_enable = cfg->wp_enable;
+ priv->vs18_enable = cfg->vs18_enable;
+
+ return 0;
+};
+
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
+ struct fsl_esdhc_plat *plat;
struct fsl_esdhc_priv *priv;
+ struct mmc *mmc;
int ret;
if (!cfg)
priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
if (!priv)
return -ENOMEM;
+ plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
+ if (!plat) {
+ free(priv);
+ return -ENOMEM;
+ }
ret = fsl_esdhc_cfg_to_priv(cfg, priv);
if (ret) {
debug("%s xlate failure\n", __func__);
+ free(plat);
free(priv);
return ret;
}
- ret = fsl_esdhc_init(priv);
+ ret = fsl_esdhc_init(priv, plat);
if (ret) {
debug("%s init failure\n", __func__);
+ free(plat);
free(priv);
return ret;
}
+ mmc = mmc_create(&plat->cfg, priv);
+ if (!mmc)
+ return -EIO;
+
+ priv->mmc = mmc;
+
return 0;
}
cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
+#endif
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
void mmc_adapter_card_type_ident(void)
return 1;
}
#endif
- do_fixup_by_compat(blob, compat, "status", "okay",
- sizeof("okay"), 1);
return 0;
}
}
#endif
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
#include <asm/arch/clock.h>
__weak void init_clk_usdhc(u32 index)
{
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
+ struct esdhc_soc_data *data =
+ (struct esdhc_soc_data *)dev_get_driver_data(dev);
+#ifdef CONFIG_DM_REGULATOR
+ struct udevice *vqmmc_dev;
+#endif
fdt_addr_t addr;
unsigned int val;
+ struct mmc *mmc;
int ret;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->esdhc_regs = (struct fsl_esdhc *)addr;
priv->dev = dev;
+ priv->mode = -1;
+ if (data) {
+ priv->flags = data->flags;
+ priv->caps = data->caps;
+ }
- val = fdtdec_get_int(fdt, node, "bus-width", -1);
+ val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
priv->bus_width = 8;
else if (val == 4)
else
priv->bus_width = 1;
- if (fdt_get_property(fdt, node, "non-removable", NULL)) {
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
+ priv->tuning_step = val;
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
+ ESDHC_TUNING_START_TAP_DEFAULT);
+ priv->tuning_start_tap = val;
+ val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
+ priv->strobe_dll_delay_target = val;
+
+ if (dev_read_bool(dev, "non-removable")) {
priv->non_removable = 1;
} else {
priv->non_removable = 0;
#ifdef CONFIG_DM_GPIO
- gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios",
- 0, &priv->cd_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN);
#endif
}
priv->wp_enable = 1;
#ifdef CONFIG_DM_GPIO
- ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0,
- &priv->wp_gpio, GPIOD_IS_IN);
+ ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+ GPIOD_IS_IN);
if (ret)
priv->wp_enable = 0;
#endif
+
+ priv->vs18_enable = 0;
+
+#ifdef CONFIG_DM_REGULATOR
+ /*
+ * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
+ * otherwise, emmc will work abnormally.
+ */
+ ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
+ if (ret) {
+ dev_dbg(dev, "no vqmmc-supply\n");
+ } else {
+ ret = regulator_set_enable(vqmmc_dev, true);
+ if (ret) {
+ dev_err(dev, "fail to enable vqmmc-supply\n");
+ return ret;
+ }
+
+ if (regulator_get_value(vqmmc_dev) == 1800000)
+ priv->vs18_enable = 1;
+ }
+#endif
+
+ if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
+ priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200);
+
/*
* TODO:
* Because lack of clk driver, if SDHC clk is not enabled,
return -EINVAL;
}
- ret = fsl_esdhc_init(priv);
+ ret = fsl_esdhc_init(priv, plat);
if (ret) {
dev_err(dev, "fsl_esdhc_init failure\n");
return ret;
}
- upriv->mmc = priv->mmc;
- priv->mmc->dev = dev;
+ mmc = &plat->mmc;
+ mmc->cfg = &plat->cfg;
+ mmc->dev = dev;
+ upriv->mmc = mmc;
- return 0;
+ return esdhc_init_common(priv, mmc);
}
+#if CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_get_cd(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return true;
+ return esdhc_getcd_common(priv);
+}
+
+static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
+}
+
+static int fsl_esdhc_set_ios(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_set_ios_common(priv, &plat->mmc);
+}
+
+static const struct dm_mmc_ops fsl_esdhc_ops = {
+ .get_cd = fsl_esdhc_get_cd,
+ .send_cmd = fsl_esdhc_send_cmd,
+ .set_ios = fsl_esdhc_set_ios,
+#ifdef MMC_SUPPORTS_TUNING
+ .execute_tuning = fsl_esdhc_execute_tuning,
+#endif
+};
+#endif
+
+static struct esdhc_soc_data usdhc_imx7d_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+ .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
+ MMC_MODE_HS_52MHz | MMC_MODE_HS,
+};
+
static const struct udevice_id fsl_esdhc_ids[] = {
{ .compatible = "fsl,imx6ul-usdhc", },
{ .compatible = "fsl,imx6sx-usdhc", },
{ .compatible = "fsl,imx6sl-usdhc", },
{ .compatible = "fsl,imx6q-usdhc", },
- { .compatible = "fsl,imx7d-usdhc", },
+ { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
{ .compatible = "fsl,imx7ulp-usdhc", },
{ .compatible = "fsl,esdhc", },
{ /* sentinel */ }
};
+#if CONFIG_IS_ENABLED(BLK)
+static int fsl_esdhc_bind(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+#endif
+
U_BOOT_DRIVER(fsl_esdhc) = {
.name = "fsl-esdhc-mmc",
.id = UCLASS_MMC,
.of_match = fsl_esdhc_ids,
+ .ops = &fsl_esdhc_ops,
+#if CONFIG_IS_ENABLED(BLK)
+ .bind = fsl_esdhc_bind,
+#endif
.probe = fsl_esdhc_probe,
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
};
#endif
projects / platform / kernel / u-boot.git / blobdiff