global: Move remaining CONFIG_SYS_* to CFG_SYS_*

[platform/kernel/u-boot.git] / drivers / fpga / virtex2.c

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 0d536f0..8871dea 100644 (file)
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -49,8 +49,8 @@
  * which yields 11.44 mS.  So let's make it bigger in order to handle
  * an XC2V1000, if anyone can ever get ahold of one.
  */
-#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT      CONFIG_SYS_HZ / 2       /* 500 ms */
+#ifndef CFG_SYS_FPGA_WAIT_INIT
+#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2       /* 500 ms */
 #endif
 
 /*
@@ -58,15 +58,15 @@
  * This is normally not necessary since for most reasonable configuration
  * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  */
-#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY      CONFIG_SYS_HZ / 200     /* 5 ms*/
+#ifndef CFG_SYS_FPGA_WAIT_BUSY
+#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200     /* 5 ms*/
 #endif
 
 /* Default timeout for waiting for FPGA to enter operational mode after
  * configuration data has been written.
  */
-#ifndef        CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG    CONFIG_SYS_HZ / 5       /* 200 ms */
+#ifndef        CFG_SYS_FPGA_WAIT_CONFIG
+#define CFG_SYS_FPGA_WAIT_CONFIG       CONFIG_SYS_HZ / 5       /* 200 ms */
 #endif
 
 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -190,9 +190,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
        udelay(10);
        ts = get_timer(0);
        do {
-               if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+               if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
                        printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
-                              __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+                              __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
                        (*fn->abort)(cookie);
                        return FPGA_FAIL;
                }
@@ -209,9 +209,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
        ts = get_timer(0);
        do {
                CONFIG_FPGA_DELAY();
-               if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+               if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
                        printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
-                              __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+                              __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
                        (*fn->abort)(cookie);
                        return FPGA_FAIL;
                }
@@ -260,9 +260,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
                                break;
                }
 
-               if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+               if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
                        printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
-                              __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+                              __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
                        (*fn->abort)(cookie);
                        ret_val = FPGA_FAIL;
                        break;
@@ -350,10 +350,10 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
                ts = get_timer(0);
                while ((*fn->busy)(cookie)) {
-                       if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+                       if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
                                printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
                                       __func__, __LINE__,
-                                      CONFIG_SYS_FPGA_WAIT_BUSY);
+                                      CFG_SYS_FPGA_WAIT_BUSY);
                                (*fn->abort)(cookie);
                                return FPGA_FAIL;
                        }