+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
-#include <clk.h>
-#include <dm/device.h>
-
#include "clk-uniphier.h"
-#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x20 + 0x200 * (ch), \
- .mask = 0x00000100, \
- .data = 0x00000100, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110 + 0x200 * (ch), \
- .mask = 0x00000001, \
- .data = 0x00000001, \
- }
-
-#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00000000, \
- .rate = 44444444, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00010000, \
- .rate = 33333333, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00020000, \
- .rate = 50000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00020000, \
- .rate = 66666666, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001000, \
- .rate = 100000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001100, \
- .rate = 40000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001200, \
- .rate = 25000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001300, \
- .rate = 22222222, \
- }
+#define UNIPHIER_MIO_CLK_SD_FIXED \
+ UNIPHIER_CLK_RATE(128, 44444444), \
+ UNIPHIER_CLK_RATE(129, 33333333), \
+ UNIPHIER_CLK_RATE(130, 50000000), \
+ UNIPHIER_CLK_RATE(131, 66666667), \
+ UNIPHIER_CLK_RATE(132, 100000000), \
+ UNIPHIER_CLK_RATE(133, 40000000), \
+ UNIPHIER_CLK_RATE(134, 25000000), \
+ UNIPHIER_CLK_RATE(135, 22222222)
-#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x20 + 0x200 * (ch), \
- .mask = 0x30000000, \
- .data = 0x30000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110 + 0x200 * (ch), \
- .mask = 0x01000000, \
- .data = 0x01000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x114 + 0x200 * (ch), \
- .mask = 0x00000001, \
- .data = 0x00000001, \
- }
+#define UNIPHIER_MIO_CLK_SD(_id, ch) \
+ { \
+ .type = UNIPHIER_CLK_TYPE_MUX, \
+ .id = (_id) + 32, \
+ .data.mux = { \
+ .parent_ids = { \
+ 128, \
+ 129, \
+ 130, \
+ 131, \
+ 132, \
+ 133, \
+ 134, \
+ 135, \
+ }, \
+ .num_parents = 8, \
+ .reg = 0x30 + 0x200 * (ch), \
+ .masks = { \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ }, \
+ .vals = { \
+ 0x00000000, \
+ 0x00010000, \
+ 0x00020000, \
+ 0x00030000, \
+ 0x00001000, \
+ 0x00001100, \
+ 0x00001200, \
+ 0x00001300, \
+ }, \
+ }, \
+ }, \
+ UNIPHIER_CLK_GATE((_id), (_id) + 32, 0x20 + 0x200 * (ch), 8)
-#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \
- { \
- .index = (idx), \
- .reg = 0x20, \
- .mask = 0x02000000, \
- .data = 0x02000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110, \
- .mask = 0x00020000, \
- .data = 0x00020000, \
- }
-
-static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
- UNIPHIER_MIO_CLK_GATE_SD(0, 0),
- UNIPHIER_MIO_CLK_GATE_SD(1, 1),
- UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */
- UNIPHIER_MIO_CLK_GATE_USB(0, 3),
- UNIPHIER_MIO_CLK_GATE_USB(1, 4),
- UNIPHIER_MIO_CLK_GATE_USB(2, 5),
- UNIPHIER_MIO_CLK_GATE_DMAC(6),
- UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */
-};
+#define UNIPHIER_MIO_CLK_USB2(id, ch) \
+ UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 28)
-static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
- UNIPHIER_MIO_CLK_RATE_SD(0, 0),
- UNIPHIER_MIO_CLK_RATE_SD(1, 1),
- UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
-};
+#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \
+ UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 29)
-static struct uniphier_clk_soc_data uniphier_mio_clk_data = {
- .gate = uniphier_mio_clk_gate,
- .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
- .rate = uniphier_mio_clk_rate,
- .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
-};
+#define UNIPHIER_MIO_CLK_DMAC(id) \
+ UNIPHIER_CLK_GATE_SIMPLE((id), 0x20, 25)
-static const struct udevice_id uniphier_mio_clk_match[] = {
- {
- .compatible = "socionext,ph1-sld3-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-ld4-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-pro4-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-sld8-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-pro5-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,proxstream2-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-ld11-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
- .compatible = "socionext,ph1-ld20-mioctrl",
- .data = (ulong)&uniphier_mio_clk_data,
- },
+const struct uniphier_clk_data uniphier_mio_clk_data[] = {
+ UNIPHIER_MIO_CLK_SD_FIXED,
+ UNIPHIER_MIO_CLK_SD(0, 0),
+ UNIPHIER_MIO_CLK_SD(1, 1),
+ UNIPHIER_MIO_CLK_SD(2, 2),
+ UNIPHIER_MIO_CLK_DMAC(7),
+ UNIPHIER_MIO_CLK_USB2(8, 0),
+ UNIPHIER_MIO_CLK_USB2(9, 1),
+ UNIPHIER_MIO_CLK_USB2(10, 2),
+ UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
+ UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
+ UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
{ /* sentinel */ }
};
-
-U_BOOT_DRIVER(uniphier_mio_clk) = {
- .name = "uniphier-mio-clk",
- .id = UCLASS_CLK,
- .of_match = uniphier_mio_clk_match,
- .probe = uniphier_clk_probe,
- .remove = uniphier_clk_remove,
- .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
- .ops = &uniphier_clk_ops,
-};
projects / platform / kernel / u-boot.git / blobdiff