rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / doc / README.m5475evb

diff --git a/doc/README.m5475evb b/doc/README.m5475evb
index 37d1438..dc9a605 100644 (file)
--- a/doc/README.m5475evb
+++ b/doc/README.m5475evb
@@ -74,20 +74,20 @@ CONFIG_M547x                -- define for all Freescale MCF547x CPUs
 CONFIG_M5475           -- define for M5475EVB board
 
 CONFIG_MCFUART         -- define to use common CF Uart driver
-CFG_UART_PORT          -- define UART port number, start with 0, 1 and 2
+CONFIG_SYS_UART_PORT           -- define UART port number, start with 0, 1 and 2
 CONFIG_BAUDRATE                -- define UART baudrate
 
 CONFIG_FSLDMAFEC       -- define to use common dma FEC driver
 CONFIG_NET_MULTI       -- define to use multi FEC in u-boot
 CONFIG_MII             -- enable to use MII driver
 CONFIG_CF_DOMII                -- enable to use MII feature in cmd_mii.c
-CFG_DISCOVER_PHY       -- enable PHY discovery
-CFG_RX_ETH_BUFFER      -- Set FEC Receive buffer
-CFG_FAULT_ECHO_LINK_DOWN--
-CFG_FEC0_PINMUX                -- Set FEC0 Pin configuration
-CFG_FEC1_PINMUX                -- Set FEC1 Pin configuration
-CFG_FEC0_MIIBASE       -- Set FEC0 MII base register
-CFG_FEC1_MIIBASE       -- Set FEC0 MII base register
+CONFIG_SYS_DISCOVER_PHY        -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER       -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX         -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX         -- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE        -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE        -- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP       -- set FEC timeout loop
 CONFIG_HAS_ETH1                -- define to enable second FEC in u-boot
 
@@ -101,35 +101,35 @@ CONFIG_SLTTMR             -- define to use SLT timer
 CONFIG_FSL_I2C         -- define to use FSL common I2C driver
 CONFIG_HARD_I2C                -- define for I2C hardware support
 CONFIG_SOFT_I2C                -- define for I2C bit-banged
-CFG_I2C_SPEED          -- define for I2C speed
-CFG_I2C_SLAVE          -- define for I2C slave address
-CFG_I2C_OFFSET         -- define for I2C base address offset
-CFG_IMMR               -- define for MBAR offset
+CONFIG_SYS_I2C_SPEED           -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE           -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET          -- define for I2C base address offset
+CONFIG_SYS_IMMR                -- define for MBAR offset
 
 CONFIG_PCI             -- define for PCI support
 CONFIG_PCI_PNP         -- define for Plug n play support
 CONFIG_SKIPPCI_HOSTBRIDGE      -- SKIP PCI Host bridge
-CFG_PCI_MEM_BUS                -- PCI memory logical offset
-CFG_PCI_MEM_PHYS       -- PCI memory physical offset
-CFG_PCI_MEM_SIZE       -- PCI memory size
-CFG_PCI_IO_BUS         -- PCI IO logical offset
-CFG_PCI_IO_PHYS                -- PCI IO physical offset
-CFG_PCI_IO_SIZE                -- PCI IO size
-CFG_PCI_CFG_BUS                -- PCI Configuration logical offset
-CFG_PCI_CFG_PHYS       -- PCI Configuration physical offset
-CFG_PCI_CFG_SIZE       -- PCI Configuration size
+CONFIG_SYS_PCI_MEM_BUS         -- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS        -- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE        -- PCI memory size
+CONFIG_SYS_PCI_IO_BUS          -- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS         -- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE         -- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS         -- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS        -- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE        -- PCI Configuration size
 
-CFG_MBAR               -- define MBAR offset
+CONFIG_SYS_MBAR                -- define MBAR offset
 
 CONFIG_MONITOR_IS_IN_RAM -- Not support
 
-CFG_INIT_RAM_ADDR      -- defines the base address of the MCF547x internal SRAM
+CONFIG_SYS_INIT_RAM_ADDR       -- defines the base address of the MCF547x internal SRAM
 
-CFG_CSn_BASE   -- defines the Chip Select Base register
-CFG_CSn_MASK   -- defines the Chip Select Mask register
-CFG_CSn_CTRL   -- defines the Chip Select Control register
+CONFIG_SYS_CSn_BASE    -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK    -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL    -- defines the Chip Select Control register
 
-CFG_SDRAM_BASE -- defines the DRAM Base
+CONFIG_SYS_SDRAM_BASE  -- defines the DRAM Base
 
 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
 ===========================================