ppc4xx: Big cleanup of PPC4xx defines

[platform/kernel/u-boot.git] / cpu / ppc4xx / speed.c

diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 34bd721..1f75137 100644 (file)
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -50,12 +50,12 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
        /*
         * Read PLL Mode register
         */
-       pllmr = mfdcr (pllmd);
+       pllmr = mfdcr (CPC0_PLLMR);
 
        /*
         * Read Pin Strapping register
         */
-       psr = mfdcr (strap);
+       psr = mfdcr (CPC0_PSR);
 
        /*
         * Determine FWD_DIV.
@@ -148,7 +148,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
                 * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
                 * to make sure it is within the proper range.
                 *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
-                * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
+                * Note freqVCO is calculated in MHz to avoid errors introduced by rounding.
                 */
                if (sysInfo->pllFwdDiv == 1) {
                        sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
@@ -205,7 +205,8 @@ ulong get_PCI_freq (void)
 
 #elif defined(CONFIG_440)
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 static u8 pll_fwdv_multi_bits[] = {
        /* values for:  1 - 16 */
        0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -279,8 +280,8 @@ void get_sys_info (sys_info_t * sysInfo)
        unsigned long plbedv0;
 
        /* Extract configured divisors */
-       mfsdr(sdr_sdstp0, strp0);
-       mfsdr(sdr_sdstp1, strp1);
+       mfsdr(SDR0_SDSTP0, strp0);
+       mfsdr(SDR0_SDSTP1, strp1);
 
        temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4);
        sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
@@ -341,7 +342,7 @@ void get_sys_info (sys_info_t *sysInfo)
        */
 
        /* Decode CPR0_PLLD0 for divisors */
-       mfcpr(clk_plld, reg);
+       mfcpr(CPR0_PLLD, reg);
        temp = (reg & PLLD_FWDVA_MASK) >> 16;
        sysInfo->pllFwdDivA = temp ? temp : 16;
        temp = (reg & PLLD_FWDVB_MASK) >> 8;
@@ -350,28 +351,28 @@ void get_sys_info (sys_info_t *sysInfo)
        sysInfo->pllFbkDiv = temp ? temp : 32;
        lfdiv = reg & PLLD_LFBDV_MASK;
 
-       mfcpr(clk_opbd, reg);
+       mfcpr(CPR0_OPBD, reg);
        temp = (reg & OPBDDV_MASK) >> 24;
        sysInfo->pllOpbDiv = temp ? temp : 4;
 
-       mfcpr(clk_perd, reg);
+       mfcpr(CPR0_PERD, reg);
        temp = (reg & PERDV_MASK) >> 24;
        sysInfo->pllExtBusDiv = temp ? temp : 8;
 
-       mfcpr(clk_primbd, reg);
+       mfcpr(CPR0_PRIMBD, reg);
        temp = (reg & PRBDV_MASK) >> 24;
        prbdv0 = temp ? temp : 8;
 
-       mfcpr(clk_spcid, reg);
+       mfcpr(CPR0_SPCID, reg);
        temp = (reg & SPCID_MASK) >> 24;
        sysInfo->pllPciDiv = temp ? temp : 4;
 
        /* Calculate 'M' based on feedback source */
-       mfsdr(sdr_sdstp0, reg);
+       mfsdr(SDR0_SDSTP0, reg);
        temp = (reg & PLLSYS0_SEL_MASK) >> 27;
        if (temp == 0) { /* PLL output */
                /* Figure which pll to use */
-               mfcpr(clk_pllc, reg);
+               mfcpr(CPR0_PLLC, reg);
                temp = (reg & PLLC_SRC_MASK) >> 29;
                if (!temp) /* PLLOUTA */
                        m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
@@ -393,7 +394,8 @@ void get_sys_info (sys_info_t *sysInfo)
        sysInfo->freqUART = sysInfo->freqPLB;
 
        /* Figure which timer source to use */
-       if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
+       if (mfspr(SPRN_CCR1) & 0x0080) {
+               /* External Clock, assume same as SYS_CLK */
                temp = sysInfo->freqProcessor / 2;  /* Max extern clock speed */
                if (CONFIG_SYS_CLK_FREQ > temp)
                        sysInfo->freqTmrClk = temp;
@@ -415,7 +417,8 @@ ulong get_PCI_freq (void)
        return sys_info.freqPCI;
 }
 
-#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) \
+       && !defined(CONFIG_XILINX_440)
 void get_sys_info (sys_info_t * sysInfo)
 {
        unsigned long strp0;
@@ -423,7 +426,7 @@ void get_sys_info (sys_info_t * sysInfo)
        unsigned long m;
 
        /* Extract configured divisors */
-       strp0 = mfdcr( cpc0_strp0 );
+       strp0 = mfdcr( CPC0_STRP0 );
        sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
        sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
        temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
@@ -448,6 +451,8 @@ void get_sys_info (sys_info_t * sysInfo)
        sysInfo->freqUART = sysInfo->freqPLB;
 }
 #else
+
+#if !defined(CONFIG_XILINX_440)
 void get_sys_info (sys_info_t * sysInfo)
 {
        unsigned long strp0;
@@ -479,8 +484,8 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 
        /* Extract configured divisors */
-       mfsdr( sdr_sdstp0,strp0 );
-       mfsdr( sdr_sdstp1,strp1 );
+       mfsdr( SDR0_SDSTP0,strp0 );
+       mfsdr( SDR0_SDSTP1,strp1 );
 
        temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
        sysInfo->pllFwdDivA = temp ? temp : 16 ;
@@ -526,7 +531,7 @@ void get_sys_info (sys_info_t * sysInfo)
        /* Determine PCI Clock Period */
        pci_clock_per = determine_pci_clock_per();
        sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
-       mfsdr(sdr_ddr0, sdr_ddrpll);
+       mfsdr(SDR0_DDR0, sdr_ddrpll);
        sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 #endif
 
@@ -534,6 +539,7 @@ void get_sys_info (sys_info_t * sysInfo)
 }
 
 #endif
+#endif /* CONFIG_XILINX_440 */
 
 #if defined(CONFIG_YUCCA)
 unsigned long determine_sysper(void)
@@ -788,8 +794,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
        /*
         * Read PLL Mode registers
         */
-       pllmr0 = mfdcr (cpc0_pllmr0);
-       pllmr1 = mfdcr (cpc0_pllmr1);
+       pllmr0 = mfdcr (CPC0_PLLMR0);
+       pllmr1 = mfdcr (CPC0_PLLMR1);
 
        /*
         * Determine forward divider A
@@ -862,6 +868,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
 
        sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;
 
+       sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
+
        sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv;
 }
 
@@ -910,8 +918,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
        /*
         * Read PLL Mode registers
         */
-       mfcpr(cprplld, cpr_plld);
-       mfcpr(cprpllc, cpr_pllc);
+       mfcpr(CPR0_PLLD, cpr_plld);
+       mfcpr(CPR0_PLLC, cpr_pllc);
 
        /*
         * Determine forward divider A
@@ -935,7 +943,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
        /*
         * Read CPR_PRIMAD register
         */
-       mfcpr(cprprimad, cpr_primad);
+       mfcpr(CPC0_PRIMAD, cpr_primad);
 
        /*
         * Determine PLB_DIV.
@@ -1066,7 +1074,7 @@ void get_sys_info (sys_info_t * sysInfo)
        };
        unsigned char sel, cpudv0, plb2xDiv;
 
-       mfcpr(cpr0_plld, tmp);
+       mfcpr(CPR0_PLLD, tmp);
 
        /*
         * Determine forward divider A
@@ -1086,29 +1094,29 @@ void get_sys_info (sys_info_t * sysInfo)
        /*
         * Determine PERDV0
         */
-       mfcpr(cpr0_perd, tmp);
+       mfcpr(CPR0_PERD, tmp);
        tmp = (tmp >> 24) & 0x03;
        sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;
 
        /*
         * Determine OPBDV0
         */
-       mfcpr(cpr0_opbd, tmp);
+       mfcpr(CPR0_OPBD, tmp);
        tmp = (tmp >> 24) & 0x03;
        sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
 
        /* Determine PLB2XDV0 */
-       mfcpr(cpr0_plbd, tmp);
+       mfcpr(CPR0_PLBD, tmp);
        tmp = (tmp >> 16) & 0x07;
        plb2xDiv = (tmp == 0) ? 8 : tmp;
 
        /* Determine CPUDV0 */
-       mfcpr(cpr0_cpud, tmp);
+       mfcpr(CPR0_CPUD, tmp);
        tmp = (tmp >> 24) & 0x07;
        cpudv0 = (tmp == 0) ? 8 : tmp;
 
        /* Determine SEL(5:7) in CPR0_PLLC */
-       mfcpr(cpr0_pllc, tmp);
+       mfcpr(CPR0_PLLC, tmp);
        sel = (tmp >> 24) & 0x07;
 
        /*