rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / cpu / mpc86xx / cpu_init.c

diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 6ed7c37..4ab88f0 100644 (file)
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -26,8 +26,13 @@
  * cpu_init.c - low level cpu init
  */
 
+#include <config.h>
 #include <common.h>
 #include <mpc86xx.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Breathe some life into the CPU...
@@ -38,74 +43,77 @@
 
 void cpu_init_f(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-       volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+       volatile immap_t    *immap = (immap_t *)CONFIG_SYS_IMMR;
        volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 
        /* Pointer is writable since we allocated a register for it */
-       gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
        /* Clear initial global data */
        memset ((void *) gd, 0, sizeof (gd_t));
 
+#ifdef CONFIG_FSL_LAW
+       init_laws();
+#endif
+
        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
         * addresses - these have to be modified later when FLASH size
         * has been determined
         */
 
-#if defined(CFG_OR0_REMAP)
-       memctl->or0 = CFG_OR0_REMAP;
+#if defined(CONFIG_SYS_OR0_REMAP)
+       memctl->or0 = CONFIG_SYS_OR0_REMAP;
 #endif
-#if defined(CFG_OR1_REMAP)
-       memctl->or1 = CFG_OR1_REMAP;
+#if defined(CONFIG_SYS_OR1_REMAP)
+       memctl->or1 = CONFIG_SYS_OR1_REMAP;
 #endif
 
        /* now restrict to preliminary range */
-#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
-       memctl->br0 = CFG_BR0_PRELIM;
-       memctl->or0 = CFG_OR0_PRELIM;
+#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
+       memctl->br0 = CONFIG_SYS_BR0_PRELIM;
+       memctl->or0 = CONFIG_SYS_OR0_PRELIM;
 #endif
 
-#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
-       memctl->or1 = CFG_OR1_PRELIM;
-       memctl->br1 = CFG_BR1_PRELIM;
+#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
+       memctl->or1 = CONFIG_SYS_OR1_PRELIM;
+       memctl->br1 = CONFIG_SYS_BR1_PRELIM;
 #endif
 
-#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
-       memctl->or2 = CFG_OR2_PRELIM;
-       memctl->br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
+       memctl->or2 = CONFIG_SYS_OR2_PRELIM;
+       memctl->br2 = CONFIG_SYS_BR2_PRELIM;
 #endif
 
-#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
-       memctl->or3 = CFG_OR3_PRELIM;
-       memctl->br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+       memctl->or3 = CONFIG_SYS_OR3_PRELIM;
+       memctl->br3 = CONFIG_SYS_BR3_PRELIM;
 #endif
 
-#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
-       memctl->or4 = CFG_OR4_PRELIM;
-       memctl->br4 = CFG_BR4_PRELIM;
+#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
+       memctl->or4 = CONFIG_SYS_OR4_PRELIM;
+       memctl->br4 = CONFIG_SYS_BR4_PRELIM;
 #endif
 
-#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
-       memctl->or5 = CFG_OR5_PRELIM;
-       memctl->br5 = CFG_BR5_PRELIM;
+#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
+       memctl->or5 = CONFIG_SYS_OR5_PRELIM;
+       memctl->br5 = CONFIG_SYS_BR5_PRELIM;
 #endif
 
-#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
-       memctl->or6 = CFG_OR6_PRELIM;
-       memctl->br6 = CFG_BR6_PRELIM;
+#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
+       memctl->or6 = CONFIG_SYS_OR6_PRELIM;
+       memctl->br6 = CONFIG_SYS_BR6_PRELIM;
 #endif
 
-#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
-       memctl->or7 = CFG_OR7_PRELIM;
-       memctl->br7 = CFG_BR7_PRELIM;
+#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
+       memctl->or7 = CONFIG_SYS_OR7_PRELIM;
+       memctl->br7 = CONFIG_SYS_BR7_PRELIM;
 #endif
 
        /* enable the timebase bit in HID0 */
        set_hid0(get_hid0() | 0x4000000);
 
-       /* enable SYNCBE | ABE bits in  HID1 */
-       set_hid1(get_hid1() | 0x00000C00);
+       /* enable EMCP, SYNCBE | ABE bits in HID1 */
+       set_hid1(get_hid1() | 0x80000C00);
 }
 
 /*
@@ -116,7 +124,25 @@ int cpu_init_r(void)
        return 0;
 }
 
-
-
-
-
+/* Set up BAT registers */
+void setup_bats(void)
+{
+       write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+       write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+       write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
+       write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
+       write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
+       write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
+       write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
+       write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
+       write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
+       write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
+       write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
+       write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
+       write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
+       write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
+       write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
+       write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
+
+       return;
+}