rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / cpu / mpc85xx / speed.c

diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d90d397..d9f9a8c 100644 (file)
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info (sys_info_t * sysInfo)
 {
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        uint plat_ratio,e500_ratio,half_freqSystemBus;
 
        plat_ratio = (gur->porpllsr) & 0x0000003e;
@@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #ifdef CONFIG_DDR_CLK_FREQ
        {
-               u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+               u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+                       >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
                if (ddr_ratio != 0x7)
                        sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
        }
@@ -65,8 +66,11 @@ void get_sys_info (sys_info_t * sysInfo)
 int get_clocks (void)
 {
        sys_info_t sys_info;
+#ifdef CONFIG_MPC8544
+       volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#endif
 #if defined(CONFIG_CPM2)
-       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+       volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
        uint sccr, dfbrg;
 
        /* set VCO = 4 * BRG */
@@ -78,8 +82,38 @@ int get_clocks (void)
        gd->cpu_clk = sys_info.freqProcessor;
        gd->bus_clk = sys_info.freqSystemBus;
        gd->mem_clk = sys_info.freqDDRBus;
+
+       /*
+        * The base clock for I2C depends on the actual SOC.  Unfortunately,
+        * there is no pattern that can be used to determine the frequency, so
+        * the only choice is to look up the actual SOC number and use the value
+        * for that SOC. This information is taken from application note
+        * AN2919.
+        */
+#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+       defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
        gd->i2c1_clk = sys_info.freqSystemBus;
-       gd->i2c2_clk = sys_info.freqSystemBus;
+#elif defined(CONFIG_MPC8544)
+       /*
+        * On the 8544, the I2C clock is the same as the SEC clock.  This can be
+        * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
+        * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
+        * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
+        * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
+        */
+       if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
+               gd->i2c1_clk = sys_info.freqSystemBus / 2;
+       else
+               gd->i2c1_clk = sys_info.freqSystemBus / 3;
+#else
+       /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
+       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+       gd->i2c2_clk = gd->i2c1_clk;
+
+#if defined(CONFIG_MPC8536)
+       gd->sdhc_clk = gd->bus_clk / 2;
+#endif
 
 #if defined(CONFIG_CPM2)
        gd->vco_out = 2*sys_info.freqSystemBus;