rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / cpu / mcf52x2 / speed.c

diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index ac860b2..fe51fb4 100644 (file)
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -23,6 +26,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/immap.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -31,11 +35,60 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int get_clocks (void)
 {
-       gd->cpu_clk = CFG_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+       volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
+       unsigned long pllcr;
+
+#ifndef CONFIG_SYS_PLL_BYPASS
+
 #ifdef CONFIG_M5249
+       /* Setup the PLL to run at the specified speed */
+#ifdef CONFIG_SYS_FAST_CLK
+       pllcr = 0x925a3100;     /* ~140MHz clock (PLL bypass = 0) */
+#else
+       pllcr = 0x135a4140;     /* ~72MHz clock (PLL bypass = 0) */
+#endif
+#endif                         /* CONFIG_M5249 */
+
+#ifdef CONFIG_M5253
+       pllcr = CONFIG_SYS_PLLCR;
+#endif                         /* CONFIG_M5253 */
+
+       cpll = cpll & 0xfffffffe;       /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
+       mbar2_writeLong(MCFSIM_PLLCR, cpll);    /* Set the PLL to bypass mode (PSTCLK = crystal) */
+       mbar2_writeLong(MCFSIM_PLLCR, pllcr);   /* set the clock speed */
+       pllcr ^= 0x00000001;    /* Set pll bypass to 1 */
+       mbar2_writeLong(MCFSIM_PLLCR, pllcr);   /* Start locking (pll bypass = 1) */
+       udelay(0x20);           /* Wait for a lock ... */
+#endif                         /* #ifndef CONFIG_SYS_PLL_BYPASS */
+
+#endif                         /* CONFIG_M5249 || CONFIG_M5253 */
+
+#if defined(CONFIG_M5275)
+       volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+
+       /* Setup PLL */
+       pll->syncr = 0x01080000;
+       while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+               ;
+       pll->syncr = 0x01000000;
+       while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+               ;
+#endif
+
+       gd->cpu_clk = CONFIG_SYS_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
        gd->bus_clk = gd->cpu_clk / 2;
 #else
        gd->bus_clk = gd->cpu_clk;
 #endif
+
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#ifdef CONFIG_SYS_I2C2_OFFSET
+       gd->i2c2_clk = gd->bus_clk;
+#endif
+#endif
+
        return (0);
 }