/* adjust memory start address for LPAE */
if (lpae) {
start[0] -= CFG_SYS_SDRAM_BASE;
- start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+ start[0] += CFG_SYS_LPAE_SDRAM_BASE;
}
if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
if (prop1 && prop2) {
initrd_start = __be64_to_cpu(*prop1);
initrd_start -= CFG_SYS_SDRAM_BASE;
- initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_start += CFG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be64_to_cpu(*prop2);
initrd_end -= CFG_SYS_SDRAM_BASE;
- initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_end += CFG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
err = fdt_delprop(blob, nodeoffset,
if (size) {
*reserve_start -= CFG_SYS_SDRAM_BASE;
*reserve_start +=
- CONFIG_SYS_LPAE_SDRAM_BASE;
+ CFG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
__cpu_to_be64(*reserve_start);
} else {