+// SPDX-License-Identifier: GPL-2.0+
/*
* Keystone : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <asm/global_data.h>
#include "board.h"
+#include <env.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
#include <spl.h>
#include <exports.h>
#include <fdt_support.h>
ddr3_size = ddr3_init();
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
- aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+ if (!(board_is_k2g_ice() || board_is_k2g_i1()))
+ aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
#endif
- if (ddr3_size)
- ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
+ if (ddr3_size)
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+ else
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
+ gd->ram_size >> 30);
+ }
return 0;
}
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-#ifndef CONFIG_DM_ETH
-int get_eth_env_param(char *env_name)
+struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
{
- char *env;
- int res = -1;
-
- env = getenv(env_name);
- if (env)
- res = simple_strtol(env, NULL, 0);
-
- return res;
+ return (struct legacy_img_hdr *)(CONFIG_TEXT_BASE);
}
-int board_eth_init(bd_t *bis)
+int board_init(void)
{
- int j;
- int res;
- int port_num;
- char link_type_name[32];
-
- if (cpu_is_k2g())
- writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
-
- /* By default, select PA PLL clock as PA clock source */
-#ifndef CONFIG_SOC_K2G
- if (psc_enable_module(KS2_LPSC_PA))
- return -1;
-#endif
- if (psc_enable_module(KS2_LPSC_CPGMAC))
- return -1;
- if (psc_enable_module(KS2_LPSC_CRYPTO))
- return -1;
-
- if (cpu_is_k2e() || cpu_is_k2l())
- pll_pa_clk_sel();
-
- port_num = get_num_eth_ports();
-
- for (j = 0; j < port_num; j++) {
- sprintf(link_type_name, "sgmii%d_link_type", j);
- res = get_eth_env_param(link_type_name);
- if (res >= 0)
- eth_priv_cfg[j].sgmii_link_type = res;
-
- keystone2_emac_initialize(ð_priv_cfg[j]);
- }
-
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
-#endif
-#endif
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
{
int lpae;
char *env;
int nbanks;
u64 size[2];
u64 start[2];
- int nodeoffset;
u32 ddr3a_size;
- int unitrd_fixup = 0;
- env = getenv("mem_lpae");
+ env = env_get("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
- env = getenv("uinitrd_fixup");
- unitrd_fixup = env && simple_strtol(env, NULL, 0);
ddr3a_size = 0;
if (lpae) {
/* adjust memory start address for LPAE */
if (lpae) {
- start[0] -= CONFIG_SYS_SDRAM_BASE;
- start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+ start[0] -= CFG_SYS_SDRAM_BASE;
+ start[0] += CFG_SYS_LPAE_SDRAM_BASE;
}
if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
}
/* reserve memory at start of bank */
- env = getenv("mem_reserve_head");
+ env = env_get("mem_reserve_head");
if (env) {
start[0] += ustrtoul(env, &endp, 0);
size[0] -= ustrtoul(env, &endp, 0);
}
- env = getenv("mem_reserve");
+ env = env_get("mem_reserve");
if (env)
size[0] -= ustrtoul(env, &endp, 0);
fdt_fixup_memory_banks(blob, start, size, nbanks);
+ return 0;
+}
+
+void ft_board_setup_ex(void *blob, struct bd_info *bd)
+{
+ int lpae;
+ u64 size;
+ char *env;
+ u64 *reserve_start;
+ int unitrd_fixup = 0;
+
+ env = env_get("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+ env = env_get("uinitrd_fixup");
+ unitrd_fixup = env && simple_strtol(env, NULL, 0);
+
/* Fix up the initrd */
if (lpae && unitrd_fixup) {
+ int nodeoffset;
int err;
- u32 *prop1, *prop2;
+ u64 *prop1, *prop2;
u64 initrd_start, initrd_end;
nodeoffset = fdt_path_offset(blob, "/chosen");
if (nodeoffset >= 0) {
- prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
+ prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
"linux,initrd-start", NULL);
- prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
+ prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
"linux,initrd-end", NULL);
if (prop1 && prop2) {
- initrd_start = __be32_to_cpu(*prop1);
- initrd_start -= CONFIG_SYS_SDRAM_BASE;
- initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_start = __be64_to_cpu(*prop1);
+ initrd_start -= CFG_SYS_SDRAM_BASE;
+ initrd_start += CFG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
- initrd_end = __be32_to_cpu(*prop2);
- initrd_end -= CONFIG_SYS_SDRAM_BASE;
- initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_end = __be64_to_cpu(*prop2);
+ initrd_end -= CFG_SYS_SDRAM_BASE;
+ initrd_end += CFG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
err = fdt_delprop(blob, nodeoffset,
}
}
- return 0;
-}
-
-void ft_board_setup_ex(void *blob, bd_t *bd)
-{
- int lpae;
- u64 size;
- char *env;
- u64 *reserve_start;
-
- env = getenv("mem_lpae");
- lpae = env && simple_strtol(env, NULL, 0);
-
if (lpae) {
/*
* the initrd and other reserved memory areas are
*reserve_start = __cpu_to_be64(*reserve_start);
size = __cpu_to_be64(*(reserve_start + 1));
if (size) {
- *reserve_start -= CONFIG_SYS_SDRAM_BASE;
+ *reserve_start -= CFG_SYS_SDRAM_BASE;
*reserve_start +=
- CONFIG_SYS_LPAE_SDRAM_BASE;
+ CFG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
__cpu_to_be64(*reserve_start);
} else {
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
#endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_DTB_RESELECT)
+int __weak embedded_dtb_select(void)
+{
+ return 0;
+}
+#endif
projects / platform / kernel / u-boot.git / blobdiff