rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / board / scb9328 / lowlevel_init.S

diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S
index ba3b6d2..8e6a49e 100644 (file)
--- a/board/scb9328/lowlevel_init.S
+++ b/board/scb9328/lowlevel_init.S
@@ -29,13 +29,13 @@ lowlevel_init:
 
 /* Change PERCLK1DIV to 14 ie 14+1 */
        ldr             r0,     =PCDR
-       ldr             r1,     =CFG_PCDR_VAL
+       ldr             r1,     =CONFIG_SYS_PCDR_VAL
        str             r1,   [r0]
 
 /* set MCU PLL Control Register 0 */
 
        ldr             r0,     =MPCTL0
-       ldr             r1,     =CFG_MPCTL0_VAL
+       ldr             r1,     =CONFIG_SYS_MPCTL0_VAL
        str             r1,   [r0]
 
 /* set mpll restart bit */
@@ -57,7 +57,7 @@ lowlevel_init:
 /* set System PLL Control Register 0 */
 
        ldr             r0,     =SPCTL0
-       ldr             r1,     =CFG_SPCTL0_VAL
+       ldr             r1,     =CONFIG_SYS_SPCTL0_VAL
        str             r1,   [r0]
 
 /* set spll restart bit */
@@ -77,7 +77,7 @@ lowlevel_init:
        bne             1b
 
        ldr             r0,   =CSCR
-       ldr             r1,   =CFG_CSCR_VAL
+       ldr             r1,   =CONFIG_SYS_CSCR_VAL
        str             r1,   [r0]
 
 /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
@@ -102,65 +102,65 @@ lowlevel_init:
        MCR p15,0,r0,c1,c0,0
 
        ldr             r0,     =GPR(0)
-       ldr             r1,     =CFG_GPR_A_VAL
+       ldr             r1,     =CONFIG_SYS_GPR_A_VAL
        str             r1,   [r0]
 
        ldr             r0,     =GIUS(0)
-       ldr             r1,     =CFG_GIUS_A_VAL
+       ldr             r1,     =CONFIG_SYS_GIUS_A_VAL
        str             r1,   [r0]
 
 /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
 
        ldr             r0,     =FMCR
-       ldr             r1,     =CFG_FMCR_VAL
+       ldr             r1,     =CONFIG_SYS_FMCR_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS0U
-       ldr             r1,     =CFG_CS0U_VAL
+       ldr             r1,     =CONFIG_SYS_CS0U_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS0L
-       ldr             r1,     =CFG_CS0L_VAL
+       ldr             r1,     =CONFIG_SYS_CS0L_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS1U
-       ldr             r1,     =CFG_CS1U_VAL
+       ldr             r1,     =CONFIG_SYS_CS1U_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS1L
-       ldr             r1,     =CFG_CS1L_VAL
+       ldr             r1,     =CONFIG_SYS_CS1L_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS2U
-       ldr             r1,     =CFG_CS2U_VAL
+       ldr             r1,     =CONFIG_SYS_CS2U_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS2L
-       ldr             r1,     =CFG_CS2L_VAL
+       ldr             r1,     =CONFIG_SYS_CS2L_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS3U
-       ldr             r1,     =CFG_CS3U_VAL
+       ldr             r1,     =CONFIG_SYS_CS3U_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS3L
-       ldr             r1,     =CFG_CS3L_VAL
+       ldr             r1,     =CONFIG_SYS_CS3L_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS4U
-       ldr             r1,     =CFG_CS4U_VAL
+       ldr             r1,     =CONFIG_SYS_CS4U_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS4L
-       ldr             r1,     =CFG_CS4L_VAL
+       ldr             r1,     =CONFIG_SYS_CS4L_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS5U
-       ldr             r1,     =CFG_CS5U_VAL
+       ldr             r1,     =CONFIG_SYS_CS5U_VAL
        str             r1,   [r0]
 
        ldr             r0,     =CS5L
-       ldr             r1,     =CFG_CS5L_VAL
+       ldr             r1,     =CONFIG_SYS_CS5L_VAL
        str             r1,   [r0]
 
 /* SDRAM Setup */