rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / board / sbc8548 / sbc8548.c

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index f31d7d6..21f82f2 100644 (file)
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -53,9 +53,9 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
-       volatile u_char *rev= (void *)CFG_BD_REV;
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+       volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
 
        printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
                        (*rev) >> 4);
@@ -98,7 +98,7 @@ initdram(int board_type)
                 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
                 */
 
-               volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+               volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
                gur->ddrdllcr = 0x81000000;
                asm("sync;isync;msync");
@@ -135,8 +135,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-       volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
        uint clkdiv;
        uint lbc_hz;
@@ -169,44 +169,44 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
 
        uint idx;
-       volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-       uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
        uint lsdmr_common;
 
        puts("    SDRAM: ");
 
-       print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+       print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
        /*
         * Setup SDRAM Base and Option Registers
         */
-       lbc->or3 = CFG_OR3_PRELIM;
+       lbc->or3 = CONFIG_SYS_OR3_PRELIM;
        asm("msync");
 
-       lbc->br3 = CFG_BR3_PRELIM;
+       lbc->br3 = CONFIG_SYS_BR3_PRELIM;
        asm("msync");
 
-       lbc->lbcr = CFG_LBC_LBCR;
+       lbc->lbcr = CONFIG_SYS_LBC_LBCR;
        asm("msync");
 
 
-       lbc->lsrt = CFG_LBC_LSRT;
-       lbc->mrtpr = CFG_LBC_MRTPR;
+       lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+       lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
        asm("msync");
 
        /*
         * MPC8548 uses "new" 15-16 style addressing.
         */
-       lsdmr_common = CFG_LBC_LSDMR_COMMON;
-       lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+       lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+       lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
 
        /*
         * Issue PRECHARGE ALL command.
         */
-       lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+       lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
        asm("sync;msync");
        *sdram_addr = 0xff;
        ppcDcbf((unsigned long) sdram_addr);
@@ -216,7 +216,7 @@ sdram_init(void)
         * Issue 8 AUTO REFRESH commands.
         */
        for (idx = 0; idx < 8; idx++) {
-               lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+               lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
                asm("sync;msync");
                *sdram_addr = 0xff;
                ppcDcbf((unsigned long) sdram_addr);
@@ -226,7 +226,7 @@ sdram_init(void)
        /*
         * Issue 8 MODE-set command.
         */
-       lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+       lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
        asm("sync;msync");
        *sdram_addr = 0xff;
        ppcDcbf((unsigned long) sdram_addr);
@@ -235,7 +235,7 @@ sdram_init(void)
        /*
         * Issue NORMAL OP command.
         */
-       lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+       lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
        asm("sync;msync");
        *sdram_addr = 0xff;
        ppcDcbf((unsigned long) sdram_addr);
@@ -244,17 +244,17 @@ sdram_init(void)
 #endif /* enable SDRAM init */
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int
 testdram(void)
 {
-       uint *pstart = (uint *) CFG_MEMTEST_START;
-       uint *pend = (uint *) CFG_MEMTEST_END;
+       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
        uint *p;
 
        printf("Testing DRAM from 0x%08x to 0x%08x\n",
-              CFG_MEMTEST_START,
-              CFG_MEMTEST_END);
+              CONFIG_SYS_MEMTEST_START,
+              CONFIG_SYS_MEMTEST_END);
 
        printf("DRAM test phase 1:\n");
        for (p = pstart; p < pend; p++)
@@ -290,9 +290,9 @@ testdram(void)
  ************************************************************************/
 long int fixed_sdram (void)
 {
-    #define CFG_DDR_CONTROL 0xc300c000
+    #define CONFIG_SYS_DDR_CONTROL 0xc300c000
 
-       volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
        ddr->cs0_bnds           = 0x0000007f;
        ddr->cs1_bnds           = 0x008000ff;
@@ -319,12 +319,12 @@ long int fixed_sdram (void)
 
        #if defined (CONFIG_DDR_ECC)
          /* Enable ECC checking */
-         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
        #else
-         ddr->sdram_cfg = CFG_DDR_CONTROL;
+         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
        #endif
 
-       return CFG_SDRAM_SIZE * 1024 * 1024;
+       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif
 
@@ -367,11 +367,11 @@ int first_free_busno=0;
 void
 pci_init_board(void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 #ifdef CONFIG_PCI1
 {
-       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
        extern void fsl_pci_init(struct pci_controller *hose);
        struct pci_controller *hose = &pci1_hose;
        struct pci_config_table *table;
@@ -397,24 +397,24 @@ pci_init_board(void)
 
                /* inbound */
                pci_set_region(hose->regions + 0,
-                              CFG_PCI_MEMORY_BUS,
-                              CFG_PCI_MEMORY_PHYS,
-                              CFG_PCI_MEMORY_SIZE,
+                              CONFIG_SYS_PCI_MEMORY_BUS,
+                              CONFIG_SYS_PCI_MEMORY_PHYS,
+                              CONFIG_SYS_PCI_MEMORY_SIZE,
                               PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 
                /* outbound memory */
                pci_set_region(hose->regions + 1,
-                              CFG_PCI1_MEM_BASE,
-                              CFG_PCI1_MEM_PHYS,
-                              CFG_PCI1_MEM_SIZE,
+                              CONFIG_SYS_PCI1_MEM_BASE,
+                              CONFIG_SYS_PCI1_MEM_PHYS,
+                              CONFIG_SYS_PCI1_MEM_SIZE,
                               PCI_REGION_MEM);
 
                /* outbound io */
                pci_set_region(hose->regions + 2,
-                              CFG_PCI1_IO_BASE,
-                              CFG_PCI1_IO_PHYS,
-                              CFG_PCI1_IO_SIZE,
+                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_PHYS,
+                              CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
                hose->region_count = 3;
 
@@ -466,7 +466,7 @@ pci_init_board(void)
 
 #ifdef CONFIG_PCIE1
 {
-       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
        extern void fsl_pci_init(struct pci_controller *hose);
        struct pci_controller *hose = &pcie1_hose;
        int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
@@ -486,23 +486,23 @@ pci_init_board(void)
 
                /* inbound */
                pci_set_region(hose->regions + 0,
-                              CFG_PCI_MEMORY_BUS,
-                              CFG_PCI_MEMORY_PHYS,
-                              CFG_PCI_MEMORY_SIZE,
+                              CONFIG_SYS_PCI_MEMORY_BUS,
+                              CONFIG_SYS_PCI_MEMORY_PHYS,
+                              CONFIG_SYS_PCI_MEMORY_SIZE,
                               PCI_REGION_MEM | PCI_REGION_MEMORY);
 
                /* outbound memory */
                pci_set_region(hose->regions + 1,
-                              CFG_PCIE1_MEM_BASE,
-                              CFG_PCIE1_MEM_PHYS,
-                              CFG_PCIE1_MEM_SIZE,
+                              CONFIG_SYS_PCIE1_MEM_BASE,
+                              CONFIG_SYS_PCIE1_MEM_PHYS,
+                              CONFIG_SYS_PCIE1_MEM_SIZE,
                               PCI_REGION_MEM);
 
                /* outbound io */
                pci_set_region(hose->regions + 2,
-                              CFG_PCIE1_IO_BASE,
-                              CFG_PCIE1_IO_PHYS,
-                              CFG_PCIE1_IO_SIZE,
+                              CONFIG_SYS_PCIE1_IO_BASE,
+                              CONFIG_SYS_PCIE1_IO_PHYS,
+                              CONFIG_SYS_PCIE1_IO_SIZE,
                               PCI_REGION_IO);
 
                hose->region_count = 3;