rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / board / sbc8349 / sbc8349.c

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 93ada0b..4154f29 100644 (file)
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -54,14 +54,14 @@ int board_early_init_f (void)
 
 phys_size_t initdram (int board_type)
 {
-       volatile immap_t *im = (immap_t *)CFG_IMMR;
+       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize = 0;
 
        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
                return -1;
 
        /* DDR SDRAM - Main SODIMM */
-       im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
        msize = spd_sdram();
 #else
@@ -88,12 +88,12 @@ phys_size_t initdram (int board_type)
  ************************************************************************/
 int fixed_sdram(void)
 {
-       volatile immap_t *im = (immap_t *)CFG_IMMR;
+       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize = 0;
        u32 ddr_size;
        u32 ddr_size_log2;
 
-       msize = CFG_DDR_SIZE;
+       msize = CONFIG_SYS_DDR_SIZE;
        for (ddr_size = msize << 20, ddr_size_log2 = 0;
             (ddr_size > 1);
             ddr_size = ddr_size>>1, ddr_size_log2++) {
@@ -101,22 +101,22 @@ int fixed_sdram(void)
                        return -1;
                }
        }
-       im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
-#if (CFG_DDR_SIZE != 256)
+#if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currently any ddr size other than 256 is not supported
 #endif
        im->ddr.csbnds[2].csbnds = 0x0000000f;
-       im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+       im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
 
        /* currently we use only one CS, so disable the other banks */
        im->ddr.cs_config[0] = 0;
        im->ddr.cs_config[1] = 0;
        im->ddr.cs_config[3] = 0;
 
-       im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-       im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+       im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+       im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 
        im->ddr.sdram_cfg =
                SDRAM_CFG_SREN
@@ -128,16 +128,16 @@ int fixed_sdram(void)
        /* for 32-bit mode burst length is 8 */
        im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
 #endif
-       im->ddr.sdram_mode = CFG_DDR_MODE;
+       im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 
-       im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+       im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
        udelay(200);
 
        /* enable DDR controller */
        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
        return msize;
 }
-#endif/*!CFG_SPD_EEPROM*/
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
 
 
 int checkboard (void)
@@ -149,44 +149,44 @@ int checkboard (void)
 /*
  * if board is fitted with SDRAM
  */
-#if defined(CFG_BR2_PRELIM)  \
-       && defined(CFG_OR2_PRELIM) \
-       && defined(CFG_LBLAWBAR2_PRELIM) \
-       && defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+       && defined(CONFIG_SYS_OR2_PRELIM) \
+       && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+       && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 /*
  * Initialize SDRAM memory on the Local Bus.
  */
 
 void sdram_init(void)
 {
-       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
        volatile lbus83xx_t *lbc= &immap->lbus;
-       uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+       uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
        puts("\n   SDRAM on Local Bus: ");
-       print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+       print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
        /*
         * Setup SDRAM Base and Option Registers, already done in cpu_init.c
         */
 
        /* setup mtrpt, lsrt and lbcr for LB bus */
-       lbc->lbcr = CFG_LBC_LBCR;
-       lbc->mrtpr = CFG_LBC_MRTPR;
-       lbc->lsrt = CFG_LBC_LSRT;
+       lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+       lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+       lbc->lsrt = CONFIG_SYS_LBC_LSRT;
        asm("sync");
 
        /*
         * Configure the SDRAM controller Machine Mode Register.
         */
-       lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 
-       lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);
 
-       lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
        asm("sync");
        /*1 times*/
        *sdram_addr = 0xff;
@@ -214,12 +214,12 @@ void sdram_init(void)
        udelay(100);
 
        /* 0x58636733; mode register write operation */
-       lbc->lsdmr = CFG_LBC_LSDMR_4;
+       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);
 
-       lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);