rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / board / pm854 / pm854.c

diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
index 90523bd..db855df 100644 (file)
--- a/board/pm854/pm854.c
+++ b/board/pm854/pm854.c
@@ -46,7 +46,7 @@ long int fixed_sdram(void);
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
+    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -83,7 +83,7 @@ initdram(int board_type)
 
 #if defined(CONFIG_DDR_DLL)
        {
-           volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+           volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
            int i,x;
 
            x = 10;
@@ -133,8 +133,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-       volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
        uint clkdiv;
        uint lbc_hz;
@@ -154,10 +154,10 @@ local_bus_init(void)
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
-               lbc->lcrr = CFG_LBC_LCRR | 0x80000000;  /* DLL Bypass */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;   /* DLL Bypass */
 
        } else if (lbc_hz >= 133) {
-               lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 
        } else {
                /*
@@ -172,7 +172,7 @@ local_bus_init(void)
                        lbc->lcrr = 0x10000004;
                }
 
-               lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
                udelay(200);
 
                /*
@@ -186,11 +186,11 @@ local_bus_init(void)
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-       uint *pstart = (uint *) CFG_MEMTEST_START;
-       uint *pend = (uint *) CFG_MEMTEST_END;
+       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
        uint *p;
 
        printf("SDRAM test phase 1:\n");
@@ -227,15 +227,15 @@ int testdram (void)
  ************************************************************************/
 long int fixed_sdram (void)
 {
-  #ifndef CFG_RAMBOOT
-       volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
-
-       ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-       ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-       ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-       ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-       ddr->sdram_mode = CFG_DDR_MODE;
-       ddr->sdram_interval = CFG_DDR_INTERVAL;
+  #ifndef CONFIG_SYS_RAMBOOT
+       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+       ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+       ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+       ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+       ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+       ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+       ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
     #if defined (CONFIG_DDR_ECC)
        ddr->err_disable = 0x0000000D;
        ddr->err_sbe = 0x00ff0000;
@@ -244,14 +244,14 @@ long int fixed_sdram (void)
        udelay(500);
     #if defined (CONFIG_DDR_ECC)
        /* Enable ECC checking */
-       ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+       ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-       ddr->sdram_cfg = CFG_DDR_CONTROL;
+       ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
        asm("sync; isync; msync");
        udelay(500);
   #endif
-       return CFG_SDRAM_SIZE * 1024 * 1024;
+       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif /* !defined(CONFIG_SPD_EEPROM) */