rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / board / matrix_vision / mvblm7 / mvblm7.c

diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c
index 3dcff67..6984af9 100644 (file)
--- a/board/matrix_vision/mvblm7/mvblm7.c
+++ b/board/matrix_vision/mvblm7/mvblm7.c
@@ -38,50 +38,50 @@
 
 int fixed_sdram(void)
 {
-       volatile immap_t *im = (immap_t *)CFG_IMMR;
+       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize = 0;
        u32 ddr_size;
        u32 ddr_size_log2;
 
-       msize = CFG_DDR_SIZE;
+       msize = CONFIG_SYS_DDR_SIZE;
        for (ddr_size = msize << 20, ddr_size_log2 = 0;
             (ddr_size > 1);
             ddr_size = ddr_size >> 1, ddr_size_log2++) {
                if (ddr_size & 1)
                        return -1;
        }
-       im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
                LAWAR_SIZE);
 
-       im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-       im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-       im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-       im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-       im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-       im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-       im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-       im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-       im->ddr.sdram_mode = CFG_DDR_MODE;
-       im->ddr.sdram_interval = CFG_DDR_INTERVAL;
-       im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+       im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+       im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+       im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+       im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+       im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+       im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+       im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+       im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+       im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+       im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 
        udelay(300);
 
        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
-       return CFG_DDR_SIZE;
+       return CONFIG_SYS_DDR_SIZE;
 }
 
 phys_size_t initdram(int board_type)
 {
-       volatile immap_t *im = (immap_t *) CFG_IMMR;
+       volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        u32 msize = 0;
 
        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
                return -1;
 
-       im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
        msize = fixed_sdram();
 
        /* return total bus RAM size(bytes) */
@@ -132,14 +132,14 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-       volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+       volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
        iopd->dat &= ~MVBLM7_MMC_CS;
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-       volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+       volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
        iopd->dat |= ~MVBLM7_MMC_CS;
 }