+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013 Keymile AG
* Valentin Longchamp <valentin.longchamp@keymile.com>
*
* Copyright 2011,2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "../common/common.h"
#include "kmp204x.h"
-DECLARE_GLOBAL_DATA_PTR;
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
int checkboard(void)
{
#define ZL30158_RST 8
-#define ZL30343_RST 9
+#define BFTIC4_RST 0
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
- /* take the Zarlinks out of reset as soon as possible */
- qrio_prst(ZL30158_RST, false, false);
- qrio_prst(ZL30343_RST, false, false);
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+ RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
- /* and set their reset to power-up only */
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
+
+ /* set the ZL30138's prstcfg to reset at power-up only */
qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
return 0;
}
invalidate_icache();
set_liodns();
- setup_portals();
+ setup_qbman_portals();
ret = trigger_fpga_config();
if (ret)
printf("error triggering PCIe FPGA config\n");
+ /* enable the Unit LED (red) & Boot LED (on) */
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
return ret;
}
return 66666666;
}
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
+
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+ /* set the ZL30343 prstcfg to reset at power-up only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
+
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
+
return 0;
}
#define NUM_SRDS_BANKS 2
-#define PHY_RST 15
int misc_init_r(void)
{
}
}
- /* take the mgmt eth phy out of reset */
- qrio_prst(PHY_RST, false, false);
-
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
#if defined(CONFIG_HUSH_INIT_VAR)
int hush_init_var(void)
{
- ivm_read_eeprom();
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
#endif
#if defined(CONFIG_LAST_STAGE_INIT)
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMCOGE4)
+ /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+ u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ env_set("actual_bank", "0");
+ }
+#endif
set_km_env();
+
return 0;
}
#endif
unsigned char mac_addr[6];
/* get the mac addr from env */
- tmp = getenv("ethaddr");
+ tmp = env_get("ethaddr");
if (!tmp) {
printf("ethaddr env variable not defined\n");
return;
}
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
- base = getenv_bootm_low();
- size = getenv_bootm_size();
+ base = env_get_bootm_low();
+ size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
- fdt_fixup_dr_usb(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_PCI
fdt_fixup_fman_ethernet(blob);
fdt_fixup_fman_mac_addresses(blob);
#endif
+
+ return 0;
}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
projects / platform / kernel / u-boot.git / blobdiff