Use correct spelling of "U-Boot"

[platform/kernel/u-boot.git] / board / freescale / mx7dsabresd / mx7dsabresd.c

diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 6c863da..fee24e2 100644 (file)
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -44,6 +44,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
        PAD_CTL_DSE_3P3V_49OHM)
 
+#define QSPI_PAD_CTRL  \
+       (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -193,6 +199,38 @@ static void iox74lv_init(void)
        gpio_direction_output(IOX_STCP, 1);
 };
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const gpmi_pads[] = {
+       MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_MCLK__NAND_WP_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+       imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+       /* NAND_USDHC_BUS_CLK is set in rom */
+       set_clk_nand();
+}
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
        MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
@@ -290,22 +328,12 @@ static struct fsl_esdhc_cfg usdhc_cfg[3] = {
        {USDHC3_BASE_ADDR},
 };
 
-static int mmc_get_env_devno(void)
+int board_mmc_get_env_dev(int devno)
 {
-       struct bootrom_sw_info **p =
-               (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-
-       u8 boot_type = (*p)->boot_dev_type;
-       u8 dev_no = (*p)->boot_dev_instance;
+       if (devno == 2)
+               devno--;
 
-       /* If not boot from sd/mmc, use default value */
-       if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
-               return CONFIG_SYS_MMC_ENV_DEV;
-
-       if (dev_no == 2)
-               dev_no--;
-
-       return dev_no;
+       return devno;
 }
 
 static int mmc_map_to_kernel_blk(int dev_no)
@@ -338,7 +366,7 @@ int board_mmc_init(bd_t *bis)
        int i, ret;
        /*
         * According to the board_mmc_init() the following map is done:
-        * (U-boot device node)    (Physical Port)
+        * (U-Boot device node)    (Physical Port)
         * mmc0                    USDHC1
         * mmc2                    USDHC3 (eMMC)
         */
@@ -394,7 +422,7 @@ static void mmc_late_init(void)
 {
        char cmd[32];
        char mmcblk[32];
-       u32 dev_no = mmc_get_env_devno();
+       u32 dev_no = mmc_get_env_dev();
 
        if (!check_mmc_autodetect())
                return;
@@ -455,6 +483,29 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+       MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+       MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+       MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+       MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+       MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+       MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+       /* Set the iomux */
+       imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+                                        ARRAY_SIZE(quadspi_pads));
+
+       /* Set the clock */
+       set_clk_qspi();
+
+       return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
@@ -477,10 +528,18 @@ int board_init(void)
        setup_fec();
 #endif
 
+#ifdef CONFIG_NAND_MXS
+       setup_gpmi_nand();
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
        setup_lcd();
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+       board_qspi_init();
+#endif
+
        return 0;
 }