Add GPL-2.0+ SPDX-License-Identifier to source files

[platform/kernel/u-boot.git] / board / freescale / mpc837xerdb / pci.c

diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
index 26e7320..8f50c93 100644 (file)
--- a/board/freescale/mpc837xerdb/pci.c
+++ b/board/freescale/mpc837xerdb/pci.c
@@ -1,59 +1,108 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <mpc83xx.h>
 #include <pci.h>
+#include <asm/io.h>
 
-#if defined(CONFIG_PCI)
 static struct pci_region pci_regions[] = {
        {
-               bus_start: CFG_PCI_MEM_BASE,
-               phys_start: CFG_PCI_MEM_PHYS,
-               size: CFG_PCI_MEM_SIZE,
+               bus_start: CONFIG_SYS_PCI_MEM_BASE,
+               phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+               size: CONFIG_SYS_PCI_MEM_SIZE,
                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
        },
        {
-               bus_start: CFG_PCI_MMIO_BASE,
-               phys_start: CFG_PCI_MMIO_PHYS,
-               size: CFG_PCI_MMIO_SIZE,
+               bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+               phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+               size: CONFIG_SYS_PCI_MMIO_SIZE,
                flags: PCI_REGION_MEM
        },
        {
-               bus_start: CFG_PCI_IO_BASE,
-               phys_start: CFG_PCI_IO_PHYS,
-               size: CFG_PCI_IO_SIZE,
+               bus_start: CONFIG_SYS_PCI_IO_BASE,
+               phys_start: CONFIG_SYS_PCI_IO_PHYS,
+               size: CONFIG_SYS_PCI_IO_SIZE,
                flags: PCI_REGION_IO
        }
 };
 
+static struct pci_region pcie_regions_0[] = {
+       {
+               .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+               .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+               .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+               .flags = PCI_REGION_MEM,
+       },
+       {
+               .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+               .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+               .size = CONFIG_SYS_PCIE1_IO_SIZE,
+               .flags = PCI_REGION_IO,
+       },
+};
+
+static struct pci_region pcie_regions_1[] = {
+       {
+               .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+               .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+               .size = CONFIG_SYS_PCIE2_MEM_SIZE,
+               .flags = PCI_REGION_MEM,
+       },
+       {
+               .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+               .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+               .size = CONFIG_SYS_PCIE2_IO_SIZE,
+               .flags = PCI_REGION_IO,
+       },
+};
+
 void pci_init_board(void)
 {
-       volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+       volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+       volatile sysconf83xx_t *sysconf = &immr->sysconf;
        volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
        volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+       volatile law83xx_t *pcie_law = sysconf->pcielaw;
        struct pci_region *reg[] = { pci_regions };
+       struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+       u32 spridr = in_be32(&immr->sysconf.spridr);
 
        /* Enable all 5 PCI_CLK_OUTPUTS */
        clk->occr |= 0xf8000000;
        udelay(2000);
 
        /* Configure PCI Local Access Windows */
-       pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+       pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
        pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 
-       pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+       pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
        pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
-       mpc83xx_pci_init(1, reg, 0);
+       mpc83xx_pci_init(1, reg);
+
+       /* There is no PEX in MPC8379 parts. */
+       if (PARTID_NO_E(spridr) == SPR_8379)
+               return;
+
+       /* Configure the clock for PCIE controller */
+       clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+                                   SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+       /* Deassert the resets in the control register */
+       out_be32(&sysconf->pecr1, 0xE0008000);
+       out_be32(&sysconf->pecr2, 0xE0008000);
+       udelay(2000);
+
+       /* Configure PCI Express Local Access Windows */
+       out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+       out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+       out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+       out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+       mpc83xx_pcie_init(2, pcie_reg);
 }
-#endif /* CONFIG_PCI */