global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

[platform/kernel/u-boot.git] / board / freescale / m5235evb / m5235evb.c

diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index 68c1631..44161a0 100644 (file)
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -1,15 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
 #include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
 #include <asm/immap.h>
 #include <asm/io.h>
 
@@ -22,7 +23,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
        gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
@@ -43,7 +44,7 @@ phys_size_t initdram(int board_type)
                GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
                GPIO_PAR_SDRAM_SDCS(3));
 
-       dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+       dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
        for (i = 0x13; i < 0x20; i++) {
                if (dramsize == (1 << i))
                        break;
@@ -60,7 +61,7 @@ phys_size_t initdram(int board_type)
 
                /* Initialize DACR0 */
                out_be32(&sdram->dacr0,
-                       SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+                       SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
                        SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
                        SDRAMC_DARCn_PS_32);
                asm("nop");
@@ -79,7 +80,7 @@ phys_size_t initdram(int board_type)
                }
 
                /* Write to this block to initiate precharge */
-               *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+               *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
 
                /*  Set RE (bit 15) in DACR */
                setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
@@ -94,10 +95,12 @@ phys_size_t initdram(int board_type)
                asm("nop");
 
                /* Write to the SDRAM Mode Register */
-               *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+               *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
        }
 
-       return dramsize;
+       gd->ram_size = dramsize;
+
+       return 0;
 };
 
 int testdram(void)