struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor0",
- CONFIG_SYS_NOR0_CSPR_EARLY,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR_EARLY,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
CFG_SYS_NOR_FTIM3
},
0,
- CONFIG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR,
0,
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR_EARLY,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR_EARLY,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK_EARLY,
CFG_SYS_NOR_CSOR,
{
CFG_SYS_NOR_FTIM3
},
0,
- CONFIG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR,
CFG_SYS_NOR_AMASK,
},
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSOR,
{
SYS_FPGA_CS_FTIM0,
SYS_FPGA_CS_FTIM1,
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSOR,
{
SYS_FPGA_CS_FTIM0,
SYS_FPGA_CS_FTIM1,
/* Read the BRDCFG54 via CLPD */
#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
+ ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
struct udevice *dev;
- ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+ ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
(void *)&brdcfg4, 1);
/* Write to the BRDCFG4 */
#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
+ ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,