struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor0",
- CONFIG_SYS_NOR0_CSPR,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR,
- CONFIG_SYS_NOR1_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
- CONFIG_SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_AMASK,
+ CFG_SYS_FPGA_CSOR,
{
- CONFIG_SYS_FPGA_FTIM0,
- CONFIG_SYS_FPGA_FTIM1,
- CONFIG_SYS_FPGA_FTIM2,
- CONFIG_SYS_FPGA_FTIM3
+ CFG_SYS_FPGA_FTIM0,
+ CFG_SYS_FPGA_FTIM1,
+ CFG_SYS_FPGA_FTIM2,
+ CFG_SYS_FPGA_FTIM3
},
}
};
},
{
"nor0",
- CONFIG_SYS_NOR0_CSPR,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR,
- CONFIG_SYS_NOR1_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
- CONFIG_SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_AMASK,
+ CFG_SYS_FPGA_CSOR,
{
- CONFIG_SYS_FPGA_FTIM0,
- CONFIG_SYS_FPGA_FTIM1,
- CONFIG_SYS_FPGA_FTIM2,
- CONFIG_SYS_FPGA_FTIM3
+ CFG_SYS_FPGA_FTIM0,
+ CFG_SYS_FPGA_FTIM1,
+ CFG_SYS_FPGA_FTIM2,
+ CFG_SYS_FPGA_FTIM3
},
}
};