global: Move remaining CONFIG_SYS_* to CFG_SYS_*

[platform/kernel/u-boot.git] / board / freescale / ls1012aqds / ls1012aqds.c

diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 2497831..194b5d2 100644 (file)
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -8,6 +9,7 @@
 #include <fdt_support.h>
 #include <asm/cache.h>
 #include <init.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
@@ -27,10 +29,10 @@
 #include <fsl_mmdc.h>
 #include <spl.h>
 #include <netdev.h>
-#include <fsl_sec.h>
 #include "../common/qixis.h"
 #include "ls1012aqds_qixis.h"
 #include "ls1012aqds_pfe.h"
+#include <net/pfe_eth/pfe/pfe_hw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -64,7 +66,7 @@ int dram_init(void)
 {
        gd->ram_size = tfa_get_dram_size();
        if (!gd->ram_size)
-               gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+               gd->ram_size = CFG_SYS_SDRAM_SIZE;
 
        return 0;
 }
@@ -88,7 +90,7 @@ int dram_init(void)
        };
 
        mmdc_init(&mparam);
-       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+       gd->ram_size = CFG_SYS_SDRAM_SIZE;
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
        /* This will break-before-make MMU for DDR */
        update_early_mmu_table();
@@ -111,11 +113,11 @@ int misc_init_r(void)
        u8 mux_sdhc_cd = 0x80;
        int bus_num = 0;
 
-#ifdef CONFIG_DM_I2C
+#if CONFIG_IS_ENABLED(DM_I2C)
        struct udevice *dev;
        int ret;
 
-       ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
+       ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR,
                                      1, &dev);
        if (ret) {
                printf("%s: Cannot find udev for a bus %d\n", __func__,
@@ -126,7 +128,7 @@ int misc_init_r(void)
 #else
        i2c_set_bus_num(bus_num);
 
-       i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+       i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
 #endif
 
        return 0;
@@ -148,20 +150,19 @@ int board_init(void)
        erratum_a010315();
 #endif
 
-#ifdef CONFIG_ENV_IS_NOWHERE
-       gd->env_addr = (ulong)&default_environment[0];
-#endif
-
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
        return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void board_quiesce_devices(void)
+{
+       pfe_command_stop(0, NULL);
+}
+#endif
+
 int esdhc_status_fixup(void *blob, const char *compat)
 {
        char esdhc0_path[] = "/soc/esdhc@1560000";
@@ -212,7 +213,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
        struct pfe_prop_val prop_val;
        void *l_blob = blob;
 
-       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+       struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
        unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
                FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
        srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -256,7 +257,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
                                                ETH_1_2_5G_MDIO_MUX);
                                prop_val.phy_mask = cpu_to_fdt32(
                                                ETH_2_5G_MDIO_PHY_MASK);
-                               prop_val.phy_mode = "sgmii-2500";
+                               prop_val.phy_mode = "2500base-x";
                                pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
                                                   ETH_1_MDIO);
                        } else {
@@ -268,7 +269,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
                                                ETH_2_2_5G_MDIO_MUX);
                                prop_val.phy_mask = cpu_to_fdt32(
                                                ETH_2_5G_MDIO_PHY_MASK);
-                               prop_val.phy_mode = "sgmii-2500";
+                               prop_val.phy_mode = "2500base-x";
                                pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
                                                   ETH_2_MDIO);
                        }
@@ -280,7 +281,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
 {
        arch_fixup_fdt(blob);