rename CFG_ macros to CONFIG_SYS

[platform/kernel/u-boot.git] / board / dave / common / fpga.c

diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c
index 5b5b5e9..30bc196 100644 (file)
--- a/board/dave/common/fpga.c
+++ b/board/dave/common/fpga.c
@@ -36,12 +36,12 @@
 
 #define MAX_ONES               226
 
-#ifdef CFG_FPGA_PRG
-# define FPGA_PRG              CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
-# define FPGA_CLK              CFG_FPGA_CLK /* FPGA clk pin (ppc output)    */
-# define FPGA_DATA             CFG_FPGA_DATA /* FPGA data pin (ppc output)  */
-# define FPGA_DONE             CFG_FPGA_DONE /* FPGA done pin (ppc input)   */
-# define FPGA_INIT             CFG_FPGA_INIT /* FPGA init pin (ppc input)   */
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG              CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_CLK              CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input)   */
 #else
 # define FPGA_PRG              0x04000000  /* FPGA program pin (ppc output) */
 # define FPGA_CLK              0x02000000  /* FPGA clk pin (ppc output)     */
@@ -74,7 +74,7 @@ static int fpga_boot (unsigned char *fpgadata, int size)
        int i, index, len;
        int count;
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
        int j;
 #else
        unsigned char b;
@@ -89,7 +89,7 @@ static int fpga_boot (unsigned char *fpgadata, int size)
                index += len + 3;
        }
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
        /* search for preamble 0xFFFFFFFF */
        while (1) {
                if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
@@ -167,7 +167,7 @@ static int fpga_boot (unsigned char *fpgadata, int size)
        DBG ("write configuration data into fpga\n");
        /* write configuration-data into fpga... */
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
        /*
         * Load uncompressed image into fpga
         */
@@ -181,7 +181,7 @@ static int fpga_boot (unsigned char *fpgadata, int size)
                        fpgadata[i] <<= 1;
                }
        }
-#else  /* ! CFG_FPGA_SPARTAN2 */
+#else  /* ! CONFIG_SYS_FPGA_SPARTAN2 */
        /* send 0xff 0x20 */
        FPGA_WRITE_1;
        FPGA_WRITE_1;
@@ -228,7 +228,7 @@ static int fpga_boot (unsigned char *fpgadata, int size)
                        FPGA_WRITE_1;
                }
        }
-#endif /* CFG_FPGA_SPARTAN2 */
+#endif /* CONFIG_SYS_FPGA_SPARTAN2 */
 
        DBG ("%s, ",
             ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");