+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Google, Inc
*
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_PCH_H
#include <pci.h>
+/* PCH types */
+#define PCH_TYPE_CPT 0x1c /* CougarPoint */
+#define PCH_TYPE_PPT 0x1e /* IvyBridge */
+
+/* PCH stepping values for LPC device */
+#define PCH_STEP_A0 0
+#define PCH_STEP_A1 1
+#define PCH_STEP_B0 2
+#define PCH_STEP_B1 3
+#define PCH_STEP_B2 4
+#define PCH_STEP_B3 5
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
#define SMBUS_IO_BASE 0x0400
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_3 0xa4
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD (1 << 2)
+#define RTC_POWER_FAILED (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
+#define BIOS_CNTL 0xDC
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT 0xb8
+
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
#define GPIO_ROUT 0xb8
-#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
-#define LPC_EN 0x82 /* LPC IF Enables Register */
-#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
-#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
-#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
-#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
-#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
-#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
-#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
-#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
-#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
-#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
-#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
-#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
-#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
-#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
-#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
-
-/* PCI Configuration Space (D31:F3): SMBus */
-#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
-#define SMB_BASE 0x20
-#define HOSTC 0x40
-#define SMB_RCV_SLVA 0x09
-
-/* HOSTC bits */
-#define I2C_EN (1 << 2)
-#define SMB_SMI_EN (1 << 1)
-#define HST_EN (1 << 0)
-
-/* SMBus I/O bits. */
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-#define SMBUS_TIMEOUT (10 * 1000 * 100)
-
-
-/* Root Complex Register Block */
-#define DEFAULT_RCBA 0xfed1c000
-#define RCB_REG(reg) (DEFAULT_RCBA + (reg))
-
-#define PCH_RCBA_BASE 0xf0
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
+#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
+#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
+
+#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
+#define IDE_SSDE1 (1 << 3)
+#define IDE_SSDE0 (1 << 2)
+#define IDE_PSDE1 (1 << 1)
+#define IDE_PSDE0 (1 << 0)
+
+#define IDE_SDMA_TIM 0x4a
+
+#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
+#define FAST_PCB1 (1 << 13)
+#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
+#define PCB1 (1 << 1)
+#define PCB0 (1 << 0)
+
+#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
+#define SATA_SP 0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define SPI_FREQ_SWSEQ 0x3893
#define SPI_DESC_COMP0 0x38b0
#define SPI_FREQ_WR_ERA 0x38b4
-#define SOFT_RESET_CTRL 0x38f4
-#define SOFT_RESET_DATA 0x38f8
#define DIR_ROUTE(a, b, c, d) \
(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR))
-#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
-#define GCS 0x3410 /* 32bit */
#define BUC 0x3414 /* 32bit */
#define PCH_DISABLE_GBE (1 << 5)
#define FD 0x3418 /* 32bit */
#define TCO2_STS 0x66
/**
- * lpc_early_init() - set up LPC serial ports and other early things
+ * pch_silicon_revision() - Read silicon device ID from the PCH
+ *
+ * @dev: PCH device
+ * @return silicon device ID
+ */
+int pch_silicon_type(struct udevice *dev);
+
+/**
+ * pch_pch_iobp_update() - Update a pch register
*
- * @blob: Device tree blob
- * @node: Offset of LPC node
- * @dev: PCH PCI device containing the LPC
- * @return 0 if OK, -ve on error
+ * @dev: PCH device
+ * @address: Address to update
+ * @andvalue: Value to AND with existing value
+ * @orvalue: Value to OR with existing value
*/
-int lpc_early_init(const void *blob, int node, pci_dev_t dev);
+void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
+ u32 orvalue);
#endif
projects / platform / kernel / u-boot.git / blobdiff