global: Move remaining CONFIG_SYS_* to CFG_SYS_*

[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc83xx / spd_sdram.c

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 6d1c6b0..4f982b8 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -59,9 +59,9 @@ void board_add_ram_info(int use_default)
 
        printf(", %s MHz)", strmhz(buf, gd->mem_clk));
 
-#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE)
        puts("\nSDRAM: ");
-       print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+       print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
 #endif
 }
 
@@ -204,12 +204,12 @@ long int spd_sdram()
                return 0;
        }
 
-#ifdef CONFIG_SYS_DDRCDR_VALUE
+#ifdef CFG_SYS_DDRCDR_VALUE
        /*
         * Adjust DDR II IO voltage biasing.  It just makes it work.
         */
        if(spd.mem_type == SPD_MEMTYPE_DDR2) {
-               immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+               immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
        }
        udelay(50000);
 #endif
@@ -693,7 +693,7 @@ long int spd_sdram()
                ddr->sdram_mode =
                        (0
                         | (1 << (16 + 10))             /* DQS Differential disable */
-#ifdef CONFIG_SYS_DDR_MODE_WEAK
+#ifdef CFG_SYS_DDR_MODE_WEAK
                         | (1 << (16 + 1))              /* weak driver (~60%) */
 #endif
                         | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
@@ -767,8 +767,8 @@ long int spd_sdram()
                debug("DDR: sdram_cfg2  = 0x%08x\n", ddr->sdram_cfg2);
        }
 
-#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL   /* Optional platform specific value */
-       ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL      /* Optional platform specific value */
+       ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
 #endif
        debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);